Lines Matching refs:vgpu_vreg
85 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); in read_vreg()
91 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); in write_vreg()
278 old = vgpu_vreg(vgpu, offset); in mul_force_wake_write()
301 vgpu_vreg(vgpu, offset) = new; in mul_force_wake_write()
302 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); in mul_force_wake_write()
313 data = vgpu_vreg(vgpu, offset); in gdrst_mmio_write()
350 vgpu_vreg(vgpu, offset) = 0; in gdrst_mmio_write()
372 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { in pch_pp_control_mmio_write()
390 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) in transconf_mmio_write()
391 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; in transconf_mmio_write()
393 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; in transconf_mmio_write()
402 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) in lcpll_ctl_mmio_write()
403 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; in lcpll_ctl_mmio_write()
405 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; in lcpll_ctl_mmio_write()
407 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) in lcpll_ctl_mmio_write()
408 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; in lcpll_ctl_mmio_write()
410 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; in lcpll_ctl_mmio_write()
423 vgpu_vreg(vgpu, offset) = 1 << 17; in dpy_reg_mmio_read()
426 vgpu_vreg(vgpu, offset) = 0x3; in dpy_reg_mmio_read()
429 vgpu_vreg(vgpu, offset) = 0x2f << 16; in dpy_reg_mmio_read()
698 data = vgpu_vreg(vgpu, offset); in pipeconf_mmio_write()
701 vgpu_vreg(vgpu, offset) |= PIPECONF_STATE_ENABLE; in pipeconf_mmio_write()
705 vgpu_vreg(vgpu, offset) &= ~PIPECONF_STATE_ENABLE; in pipeconf_mmio_write()
793 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { in ddi_buf_ctl_mmio_write()
794 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; in ddi_buf_ctl_mmio_write()
796 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; in ddi_buf_ctl_mmio_write()
807 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; in fdi_rx_iir_mmio_write()
817 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); in fdi_auto_training_started()
949 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; in dp_tp_ctl_mmio_write()
966 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | in dp_tp_status_mmio_write()
967 (vgpu_vreg(vgpu, offset) & sticky_mask); in dp_tp_status_mmio_write()
968 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); in dp_tp_status_mmio_write()
978 data = vgpu_vreg(vgpu, offset); in pch_adpa_mmio_write()
981 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; in pch_adpa_mmio_write()
991 data = vgpu_vreg(vgpu, offset); in south_chicken2_mmio_write()
994 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; in south_chicken2_mmio_write()
996 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; in south_chicken2_mmio_write()
1011 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); in pri_surf_mmio_write()
1033 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); in spr_surf_mmio_write()
1054 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); in reg50080_mmio_write()
1057 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); in reg50080_mmio_write()
1060 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC) in reg50080_mmio_write()
1110 vgpu_vreg(vgpu, reg) = value; in dp_aux_ch_ctl_trans_done()
1172 data = vgpu_vreg(vgpu, offset); in dp_aux_ch_ctl_mmio_write()
1186 vgpu_vreg(vgpu, offset) = 0; in dp_aux_ch_ctl_mmio_write()
1194 msg = vgpu_vreg(vgpu, offset + 4); in dp_aux_ch_ctl_mmio_write()
1214 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; in dp_aux_ch_ctl_mmio_write()
1231 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); in dp_aux_ch_ctl_mmio_write()
1253 vgpu_vreg(vgpu, offset + 4) = 0; in dp_aux_ch_ctl_mmio_write()
1272 vgpu_vreg(vgpu, offset + 4) = 0; in dp_aux_ch_ctl_mmio_write()
1273 vgpu_vreg(vgpu, offset + 8) = 0; in dp_aux_ch_ctl_mmio_write()
1274 vgpu_vreg(vgpu, offset + 12) = 0; in dp_aux_ch_ctl_mmio_write()
1275 vgpu_vreg(vgpu, offset + 16) = 0; in dp_aux_ch_ctl_mmio_write()
1276 vgpu_vreg(vgpu, offset + 20) = 0; in dp_aux_ch_ctl_mmio_write()
1285 vgpu_vreg(vgpu, offset + 4 * idx) = 0; in dp_aux_ch_ctl_mmio_write()
1307 vgpu_vreg(vgpu, offset + in dp_aux_ch_ctl_mmio_write()
1340 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; in vga_control_mmio_write()
1395 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, in sbi_data_mmio_read()
1408 data = vgpu_vreg(vgpu, offset); in sbi_ctl_mmio_write()
1416 vgpu_vreg(vgpu, offset) = data; in sbi_ctl_mmio_write()
1575 if (vgpu_vreg(vgpu, offset) & in power_well_ctl_mmio_write()
1577 vgpu_vreg(vgpu, offset) |= in power_well_ctl_mmio_write()
1580 vgpu_vreg(vgpu, offset) &= in power_well_ctl_mmio_write()
1590 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) in gen9_dbuf_ctl_mmio_write()
1591 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; in gen9_dbuf_ctl_mmio_write()
1593 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; in gen9_dbuf_ctl_mmio_write()
1603 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) in fpga_dbg_mmio_write()
1604 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; in fpga_dbg_mmio_write()
1615 mode = vgpu_vreg(vgpu, offset); in dma_ctrl_write()
1656 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) in dpll_status_read()
1659 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) in dpll_status_read()
1662 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) in dpll_status_read()
1665 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) in dpll_status_read()
1668 vgpu_vreg(vgpu, offset) = v; in dpll_status_read()
1786 vgpu_vreg(vgpu, offset) = v; in skl_lcpll_write()
1799 vgpu_vreg(vgpu, offset) = v; in bxt_de_pll_enable_write()
1812 vgpu_vreg(vgpu, offset) = v; in bxt_port_pll_enable_write()
1825 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; in bxt_phy_ctl_family_write()
1828 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; in bxt_phy_ctl_family_write()
1829 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; in bxt_phy_ctl_family_write()
1833 vgpu_vreg(vgpu, offset) = v; in bxt_phy_ctl_family_write()
1841 u32 v = vgpu_vreg(vgpu, offset); in bxt_port_tx_dw3_read()
1845 vgpu_vreg(vgpu, offset) = v; in bxt_port_tx_dw3_read()
1856 vgpu_vreg(vgpu, offset - 0x600) = v; in bxt_pcs_dw12_grp_write()
1857 vgpu_vreg(vgpu, offset - 0x800) = v; in bxt_pcs_dw12_grp_write()
1859 vgpu_vreg(vgpu, offset - 0x400) = v; in bxt_pcs_dw12_grp_write()
1860 vgpu_vreg(vgpu, offset - 0x600) = v; in bxt_pcs_dw12_grp_write()
1863 vgpu_vreg(vgpu, offset) = v; in bxt_pcs_dw12_grp_write()
1888 vgpu_vreg(vgpu, offset) = v; in bxt_gt_disp_pwron_write()
1896 vgpu_vreg(vgpu, offset) = 0; in edp_psr_imr_iir_write()
1923 vgpu_vreg(vgpu, offset) = lower_32_bits(pat); in bxt_ppat_low_write()
1934 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET; in guc_status_read()
1957 vgpu_vreg(vgpu, offset) = in mmio_read_from_hw()
2072 vgpu_vreg(vgpu, offset) = 0; in gvt_reg_tlb_control_handler()
2104 data = vgpu_vreg(vgpu, offset); in ring_reset_ctl_write()
2111 vgpu_vreg(vgpu, offset) = data; in ring_reset_ctl_write()
3087 old_vreg = vgpu_vreg(vgpu, offset); in intel_vgpu_mask_mmio_write()
3089 mask = vgpu_vreg(vgpu, offset) >> 16; in intel_vgpu_mask_mmio_write()
3090 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | in intel_vgpu_mask_mmio_write()
3091 (vgpu_vreg(vgpu, offset) & mask); in intel_vgpu_mask_mmio_write()
3165 old_vreg = vgpu_vreg(vgpu, offset); in intel_vgpu_mmio_reg_rw()
3177 data |= vgpu_vreg(vgpu, offset) & ro_mask; in intel_vgpu_mmio_reg_rw()
3183 u32 mask = vgpu_vreg(vgpu, offset) >> 16; in intel_vgpu_mmio_reg_rw()
3185 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) in intel_vgpu_mmio_reg_rw()
3186 | (vgpu_vreg(vgpu, offset) & mask); in intel_vgpu_mmio_reg_rw()
3217 intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset)); in mmio_pm_restore_handler()