Lines Matching refs:REG_BIT
120 #define LMEM_INIT REG_BIT(7)
121 #define DRIVERFLR REG_BIT(31)
123 #define DRIVERFLR_STATUS REG_BIT(31)
581 #define PORT_PLL_ENABLE REG_BIT(31)
582 #define PORT_PLL_LOCK REG_BIT(30)
583 #define PORT_PLL_REF_SEL REG_BIT(27)
584 #define PORT_PLL_POWER_ENABLE REG_BIT(26)
585 #define PORT_PLL_POWER_STATE REG_BIT(25)
602 #define PORT_PLL_RECALIBRATE REG_BIT(14)
603 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
621 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
636 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
957 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
960 #define CLAIM_ER_CLR REG_BIT(31)
961 #define CLAIM_ER_OVERFLOW REG_BIT(16)
1061 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */
1078 #define MBUS_JOIN REG_BIT(31)
1079 #define MBUS_HASHING_MODE_MASK REG_BIT(30)
1169 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
1173 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
1267 #define FBC_CTL_EN REG_BIT(31)
1268 #define FBC_CTL_PERIODIC REG_BIT(30)
1271 #define FBC_CTL_STOP_ON_MOD REG_BIT(15)
1272 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
1273 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
1279 #define FBC_CMD_COMPRESS REG_BIT(0)
1281 #define FBC_STAT_COMPRESSING REG_BIT(31)
1282 #define FBC_STAT_COMPRESSED REG_BIT(30)
1283 #define FBC_STAT_MODIFIED REG_BIT(29)
1286 #define FBC_CTL_FENCE_DBL REG_BIT(4)
1292 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
1298 #define FBC_MOD_NUM_VALID REG_BIT(0)
1313 #define DPFC_CTL_EN REG_BIT(31)
1314 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
1316 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
1319 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
1320 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
1321 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
1322 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
1323 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
1332 #define DPFC_RECOMP_STALL_EN REG_BIT(27)
1346 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
1347 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
1348 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
1349 #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
1350 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
1353 #define FBC_STRIDE_OVERRIDE REG_BIT(15)
1358 #define ILK_FBC_RT_VALID REG_BIT(0)
1359 #define SNB_FBC_FRONT_BUFFER REG_BIT(1)
1363 #define ILK_PABSTRETCH_DIS REG_BIT(21)
1364 #define ILK_SABSTRETCH_DIS REG_BIT(20)
1383 #define SNB_DPFC_FENCE_EN REG_BIT(29)
1396 #define FBC_REND_NUKE REG_BIT(2)
1397 #define FBC_REND_CACHE_CLEAN REG_BIT(1)
1756 #define PROCHOT_MASK REG_BIT(0)
1757 #define THERMAL_LIMIT_MASK REG_BIT(1)
1758 #define RATL_MASK REG_BIT(5)
1759 #define VR_THERMALERT_MASK REG_BIT(6)
1760 #define VR_TDC_MASK REG_BIT(7)
1761 #define POWER_LIMIT_4_MASK REG_BIT(8)
1762 #define POWER_LIMIT_1_MASK REG_BIT(10)
1763 #define POWER_LIMIT_2_MASK REG_BIT(11)
1794 #define TGL_VRH_GATING_DIS REG_BIT(31)
1795 #define DPT_GATING_DIS REG_BIT(22)
1801 #define DPCE_GATING_DIS REG_BIT(17)
1809 #define CURSOR_GATING_DIS REG_BIT(28)
1819 #define PIPEDMC_GATING_DIS REG_BIT(12)
1830 #define PIPE_CRC_ENABLE REG_BIT(31)
1875 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
1973 #define EXITLINE_ENABLE REG_BIT(31)
1983 #define VRR_CTL_VRR_ENABLE REG_BIT(31)
1984 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
1985 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
1988 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
2013 #define VRR_VMAXSHIFT_DEC REG_BIT(16)
2021 #define VRR_STATUS_VMAX_REACHED REG_BIT(31)
2022 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
2023 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
2024 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
2025 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
2026 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
2042 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
2043 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
2044 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
2067 #define TRANS_PUSH_EN REG_BIT(31)
2068 #define TRANS_PUSH_SEND REG_BIT(30)
2118 #define TGL_PSR_ERROR REG_BIT(2)
2119 #define TGL_PSR_POST_EXIT REG_BIT(1)
2120 #define TGL_PSR_PRE_ENTRY REG_BIT(0)
2184 #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */
2185 #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */
2253 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31)
2258 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
2259 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
2260 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
2265 #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
2266 #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
2267 #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
2538 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
2539 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
2540 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
2704 #define PP_ON REG_BIT(31)
2712 #define PP_READY REG_BIT(30)
2717 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27)
2734 #define EDP_FORCE_VDD REG_BIT(3)
2735 #define EDP_BLC_ENABLE REG_BIT(2)
2736 #define PANEL_POWER_RESET REG_BIT(1)
2737 #define PANEL_POWER_ON REG_BIT(0)
3423 #define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19)
3424 #define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18)
3493 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
3496 #define PIPECONF_ENABLE REG_BIT(31)
3497 #define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
3498 #define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */
3499 #define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
3502 #define PIPECONF_PIPE_LOCKED REG_BIT(25)
3503 #define PIPECONF_FORCE_BORDER REG_BIT(25)
3504 #define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
3528 #define PIPECONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
3531 #define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16)
3532 #define PIPECONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
3533 #define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13)
3538 #define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
3544 #define PIPECONF_DITHER_EN REG_BIT(4)
3630 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
3634 #define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
3635 #define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
3636 #define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
3637 #define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
3638 #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
3650 #define PIPEMISC_DITHER_ENABLE REG_BIT(4)
3668 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31)
3669 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
3674 #define PIPE_STATUS_UNDERRUN REG_BIT(31)
3675 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28)
3676 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27)
3677 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26)
3680 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
3681 #define PIPEB_HLINE_INT_EN REG_BIT(28)
3682 #define PIPEB_VBLANK_INT_EN REG_BIT(27)
3683 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
3684 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
3685 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
3686 #define PIPE_PSR_INT_EN REG_BIT(22)
3687 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
3688 #define PIPEA_HLINE_INT_EN REG_BIT(20)
3689 #define PIPEA_VBLANK_INT_EN REG_BIT(19)
3690 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
3691 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
3692 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
3693 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
3694 #define PIPEC_HLINE_INT_EN REG_BIT(12)
3695 #define PIPEC_VBLANK_INT_EN REG_BIT(11)
3696 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
3697 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
3698 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
3703 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
3704 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
3705 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
3706 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
3707 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
3708 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
3709 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
3710 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
3711 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
3712 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
3713 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
3714 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
3717 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
3718 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
3719 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
3720 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
3721 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
3722 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
3723 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
3724 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
3725 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
3726 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
3727 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
3728 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
4019 #define WM_LP_ENABLE REG_BIT(31)
4033 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
4069 #define CURSOR_ENABLE REG_BIT(31)
4070 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
4084 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
4085 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
4086 #define MCURSOR_ROTATE_180 REG_BIT(15)
4087 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
4098 #define CURSOR_POS_Y_SIGN REG_BIT(31)
4101 #define CURSOR_POS_X_SIGN REG_BIT(15)
4110 #define CUR_FBC_EN REG_BIT(31)
4139 #define DISP_ENABLE REG_BIT(31)
4140 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
4155 #define DISP_STEREO_ENABLE REG_BIT(25)
4156 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
4159 #define DISP_SRC_KEY_ENABLE REG_BIT(22)
4160 #define DISP_LINE_DOUBLE REG_BIT(20)
4161 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
4162 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
4163 #define DISP_ROTATE_180 REG_BIT(15)
4164 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
4165 #define DISP_TILED REG_BIT(10)
4166 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
4167 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
4225 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
4268 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15)
4269 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0)
4285 #define DVS_ENABLE REG_BIT(31)
4286 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
4287 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
4293 #define DVS_PIPE_CSC_ENABLE REG_BIT(24)
4294 #define DVS_SOURCE_KEY REG_BIT(22)
4295 #define DVS_RGB_ORDER_XBGR REG_BIT(20)
4296 #define DVS_YUV_FORMAT_BT709 REG_BIT(18)
4302 #define DVS_ROTATE_180 REG_BIT(15)
4303 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
4304 #define DVS_TILED REG_BIT(10)
4305 #define DVS_DEST_KEY REG_BIT(2)
4331 #define DVS_SCALE_ENABLE REG_BIT(31)
4336 #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
4337 #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
4378 #define SPRITE_ENABLE REG_BIT(31)
4379 #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
4380 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
4388 #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
4389 #define SPRITE_SOURCE_KEY REG_BIT(22)
4390 #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
4391 #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
4392 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
4398 #define SPRITE_ROTATE_180 REG_BIT(15)
4399 #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
4400 #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
4401 #define SPRITE_TILED REG_BIT(10)
4402 #define SPRITE_DEST_KEY REG_BIT(2)
4428 #define SPRITE_SCALE_ENABLE REG_BIT(31)
4433 #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
4434 #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
4478 #define SP_ENABLE REG_BIT(31)
4479 #define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
4492 #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
4493 #define SP_SOURCE_KEY REG_BIT(22)
4494 #define SP_YUV_FORMAT_BT709 REG_BIT(18)
4500 #define SP_ROTATE_180 REG_BIT(15)
4501 #define SP_TILED REG_BIT(10)
4502 #define SP_MIRROR REG_BIT(8) /* CHV pipe B */
4526 #define SP_CONST_ALPHA_ENABLE REG_BIT(31)
4625 #define PLANE_CTL_ENABLE REG_BIT(31)
4628 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
4629 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
4654 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
4658 #define PLANE_CTL_ORDER_RGBX REG_BIT(20)
4659 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
4660 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
4666 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
4667 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
4668 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
4669 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
4676 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
4677 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
4678 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
4711 #define PLANE_SURF_DECRYPT REG_BIT(2)
4738 #define PLANE_CUS_ENABLE REG_BIT(31)
4739 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
4744 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
4749 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
4757 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
4758 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
4759 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
4760 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
4761 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
4768 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
4999 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
5315 #define PRE_CSC_GAMMA_ENABLE REG_BIT(31) /* icl+ */
5316 #define POST_CSC_GAMMA_ENABLE REG_BIT(30) /* icl+ */
5317 #define PALETTE_ANTICOL_DISABLE REG_BIT(15) /* skl+ */
5491 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
5498 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
5499 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
5500 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
5501 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
5502 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
5503 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
5504 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
5505 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
5506 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
5507 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
5508 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
5538 #define DG1_MSTR_IRQ REG_BIT(31)
5539 #define DG1_MSTR_TILE(t) REG_BIT(t)
5556 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
5563 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
5609 #define IGNORE_KVMR_PIPE_A REG_BIT(23)
5610 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
5622 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
5623 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
5629 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
5674 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
5675 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
5676 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
5677 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
5678 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
5679 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
5680 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
5681 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
5682 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
5709 #define DBUF_POWER_REQUEST REG_BIT(31)
5710 #define DBUF_POWER_STATE REG_BIT(30)
5725 #define BW_BUDDY_DISABLE REG_BIT(31)
5736 #define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
5737 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
5740 #define LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
5741 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
5742 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
5743 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
5744 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
5745 #define ICL_DELAY_PMRSP REG_BIT(22)
5746 #define DISABLE_FLR_SRC REG_BIT(15)
5747 #define MASK_WAKEMEM REG_BIT(13)
5748 #define DDI_CLOCK_REG_ACCESS REG_BIT(7)
5751 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
5752 #define DCPR_MASK_LPMODE REG_BIT(26)
5753 #define DCPR_SEND_RESP_IMM REG_BIT(25)
5754 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
5788 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
5789 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
5790 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
5791 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
5792 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
5889 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
5890 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
5891 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
6210 #define TRANS_ENABLE REG_BIT(31)
6211 #define TRANS_STATE_ENABLE REG_BIT(30)
6251 #define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
6433 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
6437 #define TRANS_DP_AUDIO_ONLY REG_BIT(26)
6438 #define TRANS_DP_ENH_FRAMING REG_BIT(18)
6444 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
6445 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
6452 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
6453 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
6454 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
6571 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
6573 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
6587 #define POWER_SETUP_I1_WATTS REG_BIT(31)
6804 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
6818 #define TRANS_DDI_HDCP_SELECT REG_BIT(5)
6833 #define PORT_SYNC_MODE_ENABLE REG_BIT(4)
6838 #define DISABLE_DPT_CLK_GATING REG_BIT(1)
6887 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
7100 #define CDCLK_SQUASH_ENABLE REG_BIT(31)
7174 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
7200 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
7381 #define DC_STATE_EN_DC3CO REG_BIT(30)
7382 #define DC_STATE_DC3CO_STATUS REG_BIT(29)
7540 #define PAL_PREC_SPLIT_MODE REG_BIT(31)
7541 #define PAL_PREC_AUTO_INCREMENT REG_BIT(15)
7567 #define PRE_CSC_GAMC_AUTO_INCREMENT REG_BIT(10)
7580 #define PAL_PREC_MULTI_SEG_AUTO_INCREMENT REG_BIT(15)
7743 #define SGSI_SIDECLK_DIS REG_BIT(17)
7744 #define SGGI_DIS REG_BIT(15)
7745 #define SGR_DIS REG_BIT(13)
8089 #define TCSS_DDI_STATUS_READY REG_BIT(2)
8090 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
8091 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
8112 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
8115 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
8120 #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)