Lines Matching refs:regmap_update_bits
140 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
141 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); in meson_vid_pll_set()
204 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
208 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
211 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
213 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
215 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
219 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
221 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
223 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
226 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
231 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
267 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
269 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
293 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0); in meson_venci_cvbs_clock_config()
299 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
304 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
307 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
311 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN); in meson_venci_cvbs_clock_config()
314 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_venci_cvbs_clock_config()
317 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
321 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
325 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
329 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
331 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
335 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_venci_cvbs_clock_config()
338 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_venci_cvbs_clock_config()
510 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
526 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
528 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
539 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
569 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
573 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
587 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
591 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
594 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
598 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
602 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
605 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
609 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
613 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
616 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
817 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
819 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
821 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
885 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
887 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
894 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
898 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
903 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
907 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
912 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
916 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
921 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
925 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
930 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
934 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
938 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_vclk_set()
945 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
950 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
954 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
959 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
964 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
968 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
973 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
978 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
982 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
987 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
992 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
996 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
1001 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
1006 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
1010 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
1017 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_vclk_set()
1021 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_vclk_set()
1024 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN); in meson_vclk_set()