Lines Matching refs:gpu
17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr() argument
23 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in update_shadow_rptr()
33 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument
36 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
46 update_shadow_rptr(gpu, ring); in a5xx_flush()
63 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
66 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit_in_rb() argument
78 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a5xx_submit_in_rb()
112 a5xx_flush(gpu, ring, true); in a5xx_submit_in_rb()
113 a5xx_preempt_trigger(gpu); in a5xx_submit_in_rb()
119 a5xx_idle(gpu, ring); in a5xx_submit_in_rb()
121 msm_gpu_retire(gpu); in a5xx_submit_in_rb()
124 static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit() argument
126 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_submit()
132 gpu->cur_ctx_seqno = 0; in a5xx_submit()
133 a5xx_submit_in_rb(gpu, submit); in a5xx_submit()
167 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a5xx_submit()
187 update_shadow_rptr(gpu, ring); in a5xx_submit()
236 a5xx_flush(gpu, ring, false); in a5xx_submit()
239 a5xx_preempt_trigger(gpu); in a5xx_submit()
436 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state) in a5xx_set_hwcg() argument
438 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_set_hwcg()
454 gpu_write(gpu, regs[i].offset, in a5xx_set_hwcg()
458 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0); in a5xx_set_hwcg()
459 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_HYST_GPMU, state ? 0x00000004 : 0); in a5xx_set_hwcg()
462 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0); in a5xx_set_hwcg()
463 gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180); in a5xx_set_hwcg()
466 static int a5xx_me_init(struct msm_gpu *gpu) in a5xx_me_init() argument
468 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_me_init()
469 struct msm_ringbuffer *ring = gpu->rb[0]; in a5xx_me_init()
503 a5xx_flush(gpu, ring, true); in a5xx_me_init()
504 return a5xx_idle(gpu, ring) ? 0 : -EINVAL; in a5xx_me_init()
507 static int a5xx_preempt_start(struct msm_gpu *gpu) in a5xx_preempt_start() argument
509 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_preempt_start()
511 struct msm_ringbuffer *ring = gpu->rb[0]; in a5xx_preempt_start()
513 if (gpu->nr_rings == 1) in a5xx_preempt_start()
546 a5xx_flush(gpu, ring, false); in a5xx_preempt_start()
548 return a5xx_idle(gpu, ring) ? 0 : -EINVAL; in a5xx_preempt_start()
570 static int a5xx_ucode_init(struct msm_gpu *gpu) in a5xx_ucode_init() argument
572 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_ucode_init()
577 a5xx_gpu->pm4_bo = adreno_fw_create_bo(gpu, in a5xx_ucode_init()
584 DRM_DEV_ERROR(gpu->dev->dev, "could not allocate PM4: %d\n", in a5xx_ucode_init()
593 a5xx_gpu->pfp_bo = adreno_fw_create_bo(gpu, in a5xx_ucode_init()
599 DRM_DEV_ERROR(gpu->dev->dev, "could not allocate PFP: %d\n", in a5xx_ucode_init()
608 gpu_write64(gpu, REG_A5XX_CP_ME_INSTR_BASE_LO, a5xx_gpu->pm4_iova); in a5xx_ucode_init()
610 gpu_write64(gpu, REG_A5XX_CP_PFP_INSTR_BASE_LO, a5xx_gpu->pfp_iova); in a5xx_ucode_init()
617 static int a5xx_zap_shader_resume(struct msm_gpu *gpu) in a5xx_zap_shader_resume() argument
619 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_zap_shader_resume()
632 gpu->name, ret); in a5xx_zap_shader_resume()
637 static int a5xx_zap_shader_init(struct msm_gpu *gpu) in a5xx_zap_shader_init() argument
647 return a5xx_zap_shader_resume(gpu); in a5xx_zap_shader_init()
649 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); in a5xx_zap_shader_init()
668 static int a5xx_hw_init(struct msm_gpu *gpu) in a5xx_hw_init() argument
670 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_hw_init()
675 gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); in a5xx_hw_init()
679 gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); in a5xx_hw_init()
682 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF); in a5xx_hw_init()
685 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001); in a5xx_hw_init()
693 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11, in a5xx_hw_init()
695 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12, in a5xx_hw_init()
697 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13, in a5xx_hw_init()
699 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14, in a5xx_hw_init()
701 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15, in a5xx_hw_init()
703 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16, in a5xx_hw_init()
705 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17, in a5xx_hw_init()
707 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18, in a5xx_hw_init()
712 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL, in a5xx_hw_init()
716 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_CNTL, 0x01); in a5xx_hw_init()
719 gpu_write(gpu, REG_A5XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); in a5xx_hw_init()
722 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0, 6); in a5xx_hw_init()
725 gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02); in a5xx_hw_init()
728 gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, 0xFFFF0000); in a5xx_hw_init()
729 gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, 0x0001FFFF); in a5xx_hw_init()
730 gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, 0xFFFF0000); in a5xx_hw_init()
731 gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, 0x0001FFFF); in a5xx_hw_init()
734 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000); in a5xx_hw_init()
735 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000); in a5xx_hw_init()
736 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO, in a5xx_hw_init()
738 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); in a5xx_hw_init()
742 gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20); in a5xx_hw_init()
744 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); in a5xx_hw_init()
746 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20); in a5xx_hw_init()
747 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030); in a5xx_hw_init()
748 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A); in a5xx_hw_init()
750 gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40); in a5xx_hw_init()
752 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40); in a5xx_hw_init()
754 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); in a5xx_hw_init()
755 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060); in a5xx_hw_init()
756 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16); in a5xx_hw_init()
760 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
764 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
767 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
771 gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); in a5xx_hw_init()
779 gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); in a5xx_hw_init()
782 gpu_write(gpu, REG_A5XX_UCHE_MODE_CNTL, BIT(29)); in a5xx_hw_init()
785 gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); in a5xx_hw_init()
788 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL1, 0xA6FFFFFF); in a5xx_hw_init()
801 gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, (1 << 11), 0); in a5xx_hw_init()
804 a5xx_set_hwcg(gpu, true); in a5xx_hw_init()
806 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F); in a5xx_hw_init()
814 gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, regbit << 7); in a5xx_hw_init()
815 gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, regbit << 1); in a5xx_hw_init()
819 gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, regbit); in a5xx_hw_init()
822 gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, (1 << 10)); in a5xx_hw_init()
825 gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007); in a5xx_hw_init()
828 gpu_write(gpu, REG_A5XX_CP_PROTECT(0), ADRENO_PROTECT_RW(0x04, 4)); in a5xx_hw_init()
829 gpu_write(gpu, REG_A5XX_CP_PROTECT(1), ADRENO_PROTECT_RW(0x08, 8)); in a5xx_hw_init()
830 gpu_write(gpu, REG_A5XX_CP_PROTECT(2), ADRENO_PROTECT_RW(0x10, 16)); in a5xx_hw_init()
831 gpu_write(gpu, REG_A5XX_CP_PROTECT(3), ADRENO_PROTECT_RW(0x20, 32)); in a5xx_hw_init()
832 gpu_write(gpu, REG_A5XX_CP_PROTECT(4), ADRENO_PROTECT_RW(0x40, 64)); in a5xx_hw_init()
833 gpu_write(gpu, REG_A5XX_CP_PROTECT(5), ADRENO_PROTECT_RW(0x80, 64)); in a5xx_hw_init()
836 gpu_write(gpu, REG_A5XX_CP_PROTECT(6), in a5xx_hw_init()
839 gpu_write(gpu, REG_A5XX_CP_PROTECT(7), in a5xx_hw_init()
843 gpu_write(gpu, REG_A5XX_CP_PROTECT(8), ADRENO_PROTECT_RW(0x800, 64)); in a5xx_hw_init()
844 gpu_write(gpu, REG_A5XX_CP_PROTECT(9), ADRENO_PROTECT_RW(0x840, 8)); in a5xx_hw_init()
845 gpu_write(gpu, REG_A5XX_CP_PROTECT(10), ADRENO_PROTECT_RW(0x880, 32)); in a5xx_hw_init()
846 gpu_write(gpu, REG_A5XX_CP_PROTECT(11), ADRENO_PROTECT_RW(0xAA0, 1)); in a5xx_hw_init()
849 gpu_write(gpu, REG_A5XX_CP_PROTECT(12), ADRENO_PROTECT_RW(0xCC0, 1)); in a5xx_hw_init()
850 gpu_write(gpu, REG_A5XX_CP_PROTECT(13), ADRENO_PROTECT_RW(0xCF0, 2)); in a5xx_hw_init()
853 gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8)); in a5xx_hw_init()
854 gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 16)); in a5xx_hw_init()
857 gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); in a5xx_hw_init()
860 gpu_write(gpu, REG_A5XX_CP_PROTECT(17), in a5xx_hw_init()
863 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_CNTL, 0); in a5xx_hw_init()
869 gpu_write64(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, 0x00000000); in a5xx_hw_init()
870 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); in a5xx_hw_init()
873 gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
874 gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
875 gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
876 gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
877 gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
878 gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
879 gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
880 gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
881 gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
882 gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
883 gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
884 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
892 gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, BIT(23)); in a5xx_hw_init()
893 gpu_rmw(gpu, REG_A5XX_HLSQ_DBG_ECO_CNTL, BIT(18), 0); in a5xx_hw_init()
896 ret = adreno_hw_init(gpu); in a5xx_hw_init()
901 a5xx_gpmu_ucode_init(gpu); in a5xx_hw_init()
903 ret = a5xx_ucode_init(gpu); in a5xx_hw_init()
908 gpu_write64(gpu, REG_A5XX_CP_RB_BASE, gpu->rb[0]->iova); in a5xx_hw_init()
916 gpu_write(gpu, REG_A5XX_CP_RB_CNTL, in a5xx_hw_init()
922 a5xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, in a5xx_hw_init()
923 sizeof(u32) * gpu->nr_rings, in a5xx_hw_init()
925 gpu->aspace, &a5xx_gpu->shadow_bo, in a5xx_hw_init()
934 gpu_write64(gpu, REG_A5XX_CP_RB_RPTR_ADDR, in a5xx_hw_init()
935 shadowptr(a5xx_gpu, gpu->rb[0])); in a5xx_hw_init()
936 } else if (gpu->nr_rings > 1) { in a5xx_hw_init()
938 a5xx_preempt_fini(gpu); in a5xx_hw_init()
939 gpu->nr_rings = 1; in a5xx_hw_init()
942 a5xx_preempt_hw_init(gpu); in a5xx_hw_init()
945 gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK, A5XX_INT_MASK); in a5xx_hw_init()
948 gpu_write(gpu, REG_A5XX_CP_PFP_ME_CNTL, 0); in a5xx_hw_init()
949 ret = a5xx_me_init(gpu); in a5xx_hw_init()
953 ret = a5xx_power_init(gpu); in a5xx_hw_init()
962 OUT_PKT7(gpu->rb[0], CP_EVENT_WRITE, 1); in a5xx_hw_init()
963 OUT_RING(gpu->rb[0], CP_EVENT_WRITE_0_EVENT(STAT_EVENT)); in a5xx_hw_init()
965 a5xx_flush(gpu, gpu->rb[0], true); in a5xx_hw_init()
966 if (!a5xx_idle(gpu, gpu->rb[0])) in a5xx_hw_init()
978 ret = a5xx_zap_shader_init(gpu); in a5xx_hw_init()
980 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); in a5xx_hw_init()
981 OUT_RING(gpu->rb[0], 0x00000000); in a5xx_hw_init()
983 a5xx_flush(gpu, gpu->rb[0], true); in a5xx_hw_init()
984 if (!a5xx_idle(gpu, gpu->rb[0])) in a5xx_hw_init()
993 dev_warn_once(gpu->dev->dev, in a5xx_hw_init()
995 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0); in a5xx_hw_init()
1001 a5xx_preempt_start(gpu); in a5xx_hw_init()
1006 static void a5xx_recover(struct msm_gpu *gpu) in a5xx_recover() argument
1010 adreno_dump_info(gpu); in a5xx_recover()
1014 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i))); in a5xx_recover()
1018 a5xx_dump(gpu); in a5xx_recover()
1020 gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 1); in a5xx_recover()
1021 gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); in a5xx_recover()
1022 gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 0); in a5xx_recover()
1023 adreno_recover(gpu); in a5xx_recover()
1026 static void a5xx_destroy(struct msm_gpu *gpu) in a5xx_destroy() argument
1028 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_destroy()
1031 DBG("%s", gpu->name); in a5xx_destroy()
1033 a5xx_preempt_fini(gpu); in a5xx_destroy()
1036 msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->aspace); in a5xx_destroy()
1041 msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->aspace); in a5xx_destroy()
1046 msm_gem_unpin_iova(a5xx_gpu->gpmu_bo, gpu->aspace); in a5xx_destroy()
1051 msm_gem_unpin_iova(a5xx_gpu->shadow_bo, gpu->aspace); in a5xx_destroy()
1059 static inline bool _a5xx_check_idle(struct msm_gpu *gpu) in _a5xx_check_idle() argument
1061 if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY) in _a5xx_check_idle()
1068 return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) & in _a5xx_check_idle()
1072 bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a5xx_idle() argument
1074 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_idle()
1083 if (!adreno_idle(gpu, ring)) in a5xx_idle()
1086 if (spin_until(_a5xx_check_idle(gpu))) { in a5xx_idle()
1088 gpu->name, __builtin_return_address(0), in a5xx_idle()
1089 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_idle()
1090 gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS), in a5xx_idle()
1091 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_idle()
1092 gpu_read(gpu, REG_A5XX_CP_RB_WPTR)); in a5xx_idle()
1101 struct msm_gpu *gpu = arg; in a5xx_fault_handler() local
1104 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(4)), in a5xx_fault_handler()
1105 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(5)), in a5xx_fault_handler()
1106 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(6)), in a5xx_fault_handler()
1107 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(7))); in a5xx_fault_handler()
1112 static void a5xx_cp_err_irq(struct msm_gpu *gpu) in a5xx_cp_err_irq() argument
1114 u32 status = gpu_read(gpu, REG_A5XX_CP_INTERRUPT_STATUS); in a5xx_cp_err_irq()
1119 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, 0); in a5xx_cp_err_irq()
1126 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA); in a5xx_cp_err_irq()
1127 val = gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA); in a5xx_cp_err_irq()
1129 dev_err_ratelimited(gpu->dev->dev, "CP | opcode error | possible opcode=0x%8.8X\n", in a5xx_cp_err_irq()
1134 dev_err_ratelimited(gpu->dev->dev, "CP | HW fault | status=0x%8.8X\n", in a5xx_cp_err_irq()
1135 gpu_read(gpu, REG_A5XX_CP_HW_FAULT)); in a5xx_cp_err_irq()
1138 dev_err_ratelimited(gpu->dev->dev, "CP | DMA error\n"); in a5xx_cp_err_irq()
1141 u32 val = gpu_read(gpu, REG_A5XX_CP_PROTECT_STATUS); in a5xx_cp_err_irq()
1143 dev_err_ratelimited(gpu->dev->dev, in a5xx_cp_err_irq()
1150 u32 status = gpu_read(gpu, REG_A5XX_CP_AHB_FAULT); in a5xx_cp_err_irq()
1156 dev_err_ratelimited(gpu->dev->dev, in a5xx_cp_err_irq()
1163 static void a5xx_rbbm_err_irq(struct msm_gpu *gpu, u32 status) in a5xx_rbbm_err_irq() argument
1166 u32 val = gpu_read(gpu, REG_A5XX_RBBM_AHB_ERROR_STATUS); in a5xx_rbbm_err_irq()
1168 dev_err_ratelimited(gpu->dev->dev, in a5xx_rbbm_err_irq()
1175 gpu_write(gpu, REG_A5XX_RBBM_AHB_CMD, (1 << 4)); in a5xx_rbbm_err_irq()
1178 gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD, in a5xx_rbbm_err_irq()
1183 dev_err_ratelimited(gpu->dev->dev, "RBBM | AHB transfer timeout\n"); in a5xx_rbbm_err_irq()
1186 dev_err_ratelimited(gpu->dev->dev, "RBBM | ME master split | status=0x%X\n", in a5xx_rbbm_err_irq()
1187 gpu_read(gpu, REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS)); in a5xx_rbbm_err_irq()
1190 dev_err_ratelimited(gpu->dev->dev, "RBBM | PFP master split | status=0x%X\n", in a5xx_rbbm_err_irq()
1191 gpu_read(gpu, REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS)); in a5xx_rbbm_err_irq()
1194 dev_err_ratelimited(gpu->dev->dev, "RBBM | ETS master split | status=0x%X\n", in a5xx_rbbm_err_irq()
1195 gpu_read(gpu, REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS)); in a5xx_rbbm_err_irq()
1198 dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB ASYNC overflow\n"); in a5xx_rbbm_err_irq()
1201 dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB bus overflow\n"); in a5xx_rbbm_err_irq()
1204 static void a5xx_uche_err_irq(struct msm_gpu *gpu) in a5xx_uche_err_irq() argument
1206 uint64_t addr = (uint64_t) gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_HI); in a5xx_uche_err_irq()
1208 addr |= gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_LO); in a5xx_uche_err_irq()
1210 dev_err_ratelimited(gpu->dev->dev, "UCHE | Out of bounds access | addr=0x%llX\n", in a5xx_uche_err_irq()
1214 static void a5xx_gpmu_err_irq(struct msm_gpu *gpu) in a5xx_gpmu_err_irq() argument
1216 dev_err_ratelimited(gpu->dev->dev, "GPMU | voltage droop\n"); in a5xx_gpmu_err_irq()
1219 static void a5xx_fault_detect_irq(struct msm_gpu *gpu) in a5xx_fault_detect_irq() argument
1221 struct drm_device *dev = gpu->dev; in a5xx_fault_detect_irq()
1222 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); in a5xx_fault_detect_irq()
1230 if (gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24)) in a5xx_fault_detect_irq()
1235 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_fault_detect_irq()
1236 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_fault_detect_irq()
1237 gpu_read(gpu, REG_A5XX_CP_RB_WPTR), in a5xx_fault_detect_irq()
1238 gpu_read64(gpu, REG_A5XX_CP_IB1_BASE), in a5xx_fault_detect_irq()
1239 gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ), in a5xx_fault_detect_irq()
1240 gpu_read64(gpu, REG_A5XX_CP_IB2_BASE), in a5xx_fault_detect_irq()
1241 gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ)); in a5xx_fault_detect_irq()
1244 del_timer(&gpu->hangcheck_timer); in a5xx_fault_detect_irq()
1246 kthread_queue_work(gpu->worker, &gpu->recover_work); in a5xx_fault_detect_irq()
1257 static irqreturn_t a5xx_irq(struct msm_gpu *gpu) in a5xx_irq() argument
1259 struct msm_drm_private *priv = gpu->dev->dev_private; in a5xx_irq()
1260 u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS); in a5xx_irq()
1266 gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD, in a5xx_irq()
1276 a5xx_rbbm_err_irq(gpu, status); in a5xx_irq()
1279 a5xx_cp_err_irq(gpu); in a5xx_irq()
1282 a5xx_fault_detect_irq(gpu); in a5xx_irq()
1285 a5xx_uche_err_irq(gpu); in a5xx_irq()
1288 a5xx_gpmu_err_irq(gpu); in a5xx_irq()
1291 a5xx_preempt_trigger(gpu); in a5xx_irq()
1292 msm_gpu_retire(gpu); in a5xx_irq()
1296 a5xx_preempt_irq(gpu); in a5xx_irq()
1332 static void a5xx_dump(struct msm_gpu *gpu) in a5xx_dump() argument
1334 DRM_DEV_INFO(gpu->dev->dev, "status: %08x\n", in a5xx_dump()
1335 gpu_read(gpu, REG_A5XX_RBBM_STATUS)); in a5xx_dump()
1336 adreno_dump(gpu); in a5xx_dump()
1339 static int a5xx_pm_resume(struct msm_gpu *gpu) in a5xx_pm_resume() argument
1341 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_pm_resume()
1345 ret = msm_gpu_pm_resume(gpu); in a5xx_pm_resume()
1352 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0x00000055); in a5xx_pm_resume()
1353 a5xx_set_hwcg(gpu, true); in a5xx_pm_resume()
1355 gpu_rmw(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0xff, 0); in a5xx_pm_resume()
1360 gpu_write(gpu, REG_A5XX_GPMU_RBCCU_POWER_CNTL, 0x778000); in a5xx_pm_resume()
1365 ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS, in a5xx_pm_resume()
1369 gpu->name, in a5xx_pm_resume()
1370 gpu_read(gpu, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS)); in a5xx_pm_resume()
1375 gpu_write(gpu, REG_A5XX_GPMU_SP_POWER_CNTL, 0x778000); in a5xx_pm_resume()
1376 ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_SP_PWR_CLK_STATUS, in a5xx_pm_resume()
1380 gpu->name); in a5xx_pm_resume()
1385 static int a5xx_pm_suspend(struct msm_gpu *gpu) in a5xx_pm_suspend() argument
1387 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_pm_suspend()
1398 gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, mask); in a5xx_pm_suspend()
1399 spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) & in a5xx_pm_suspend()
1402 gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0); in a5xx_pm_suspend()
1409 gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000); in a5xx_pm_suspend()
1410 gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000); in a5xx_pm_suspend()
1413 ret = msm_gpu_pm_suspend(gpu); in a5xx_pm_suspend()
1418 for (i = 0; i < gpu->nr_rings; i++) in a5xx_pm_suspend()
1424 static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) in a5xx_get_timestamp() argument
1426 *value = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO); in a5xx_get_timestamp()
1442 static int a5xx_crashdumper_init(struct msm_gpu *gpu, in a5xx_crashdumper_init() argument
1445 dumper->ptr = msm_gem_kernel_new(gpu->dev, in a5xx_crashdumper_init()
1446 SZ_1M, MSM_BO_WC, gpu->aspace, in a5xx_crashdumper_init()
1455 static int a5xx_crashdumper_run(struct msm_gpu *gpu, in a5xx_crashdumper_run() argument
1463 gpu_write64(gpu, REG_A5XX_CP_CRASH_SCRIPT_BASE_LO, dumper->iova); in a5xx_crashdumper_run()
1465 gpu_write(gpu, REG_A5XX_CP_CRASH_DUMP_CNTL, 1); in a5xx_crashdumper_run()
1467 return gpu_poll_timeout(gpu, REG_A5XX_CP_CRASH_DUMP_CNTL, val, in a5xx_crashdumper_run()
1498 static void a5xx_gpu_state_get_hlsq_regs(struct msm_gpu *gpu, in a5xx_gpu_state_get_hlsq_regs() argument
1506 if (a5xx_crashdumper_init(gpu, &dumper)) in a5xx_gpu_state_get_hlsq_regs()
1544 if (a5xx_crashdumper_run(gpu, &dumper)) { in a5xx_gpu_state_get_hlsq_regs()
1546 msm_gem_kernel_put(dumper.bo, gpu->aspace); in a5xx_gpu_state_get_hlsq_regs()
1554 msm_gem_kernel_put(dumper.bo, gpu->aspace); in a5xx_gpu_state_get_hlsq_regs()
1557 static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu) in a5xx_gpu_state_get() argument
1561 bool stalled = !!(gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24)); in a5xx_gpu_state_get()
1567 a5xx_set_hwcg(gpu, false); in a5xx_gpu_state_get()
1570 adreno_gpu_state_get(gpu, &(a5xx_state->base)); in a5xx_gpu_state_get()
1572 a5xx_state->base.rbbm_status = gpu_read(gpu, REG_A5XX_RBBM_STATUS); in a5xx_gpu_state_get()
1580 a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state); in a5xx_gpu_state_get()
1582 a5xx_set_hwcg(gpu, true); in a5xx_gpu_state_get()
1610 static void a5xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, in a5xx_show() argument
1621 adreno_show(gpu, state, p); in a5xx_show()
1651 static struct msm_ringbuffer *a5xx_active_ring(struct msm_gpu *gpu) in a5xx_active_ring() argument
1653 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_active_ring()
1659 static u64 a5xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) in a5xx_gpu_busy() argument
1663 busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO); in a5xx_gpu_busy()
1664 *out_sample_rate = clk_get_rate(gpu->core_clk); in a5xx_gpu_busy()
1669 static uint32_t a5xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a5xx_get_rptr() argument
1671 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_get_rptr()
1677 return ring->memptrs->rptr = gpu_read(gpu, REG_A5XX_CP_RB_RPTR); in a5xx_get_rptr()
1745 struct msm_gpu *gpu; in a5xx_gpu_init() local
1758 gpu = &adreno_gpu->base; in a5xx_gpu_init()
1772 if (gpu->aspace) in a5xx_gpu_init()
1773 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a5xx_fault_handler); in a5xx_gpu_init()
1776 a5xx_preempt_init(gpu); in a5xx_gpu_init()
1778 return gpu; in a5xx_gpu_init()