Lines Matching refs:gpu
18 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle() argument
20 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_check_idle()
28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
32 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
36 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle() argument
39 if (!adreno_idle(gpu, ring)) in a6xx_idle()
42 if (spin_until(_a6xx_check_idle(gpu))) { in a6xx_idle()
44 gpu->name, __builtin_return_address(0), in a6xx_idle()
45 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle()
47 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_idle()
48 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a6xx_idle()
55 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr() argument
57 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in update_shadow_rptr()
68 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_flush() argument
73 update_shadow_rptr(gpu, ring); in a6xx_flush()
88 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); in a6xx_flush()
172 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a6xx_submit() argument
175 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_submit()
206 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) in a6xx_submit()
226 update_shadow_rptr(gpu, ring); in a6xx_submit()
250 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO)); in a6xx_submit()
252 a6xx_flush(gpu, ring); in a6xx_submit()
591 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) in a6xx_set_hwcg() argument
593 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_set_hwcg()
608 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); in a6xx_set_hwcg()
618 gpu_write(gpu, reg->offset, state ? reg->value : 0); in a6xx_set_hwcg()
623 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); in a6xx_set_hwcg()
750 static void a6xx_set_cp_protect(struct msm_gpu *gpu) in a6xx_set_cp_protect() argument
752 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_set_cp_protect()
778 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3)); in a6xx_set_cp_protect()
781 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]); in a6xx_set_cp_protect()
783 gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]); in a6xx_set_cp_protect()
786 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) in a6xx_set_ubwc_config() argument
788 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_set_ubwc_config()
816 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, in a6xx_set_ubwc_config()
818 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); in a6xx_set_ubwc_config()
819 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, in a6xx_set_ubwc_config()
821 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); in a6xx_set_ubwc_config()
824 static int a6xx_cp_init(struct msm_gpu *gpu) in a6xx_cp_init() argument
826 struct msm_ringbuffer *ring = gpu->rb[0]; in a6xx_cp_init()
849 a6xx_flush(gpu, ring); in a6xx_cp_init()
850 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; in a6xx_cp_init()
861 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_ucode_check_version() local
897 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_ucode_check_version()
906 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_ucode_check_version()
912 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_ucode_check_version()
920 static int a6xx_ucode_init(struct msm_gpu *gpu) in a6xx_ucode_init() argument
922 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_ucode_init()
926 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, in a6xx_ucode_init()
933 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_ucode_init()
941 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); in a6xx_ucode_init()
949 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); in a6xx_ucode_init()
954 static int a6xx_zap_shader_init(struct msm_gpu *gpu) in a6xx_zap_shader_init() argument
962 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); in a6xx_zap_shader_init()
980 static int hw_init(struct msm_gpu *gpu) in hw_init() argument
982 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in hw_init()
991 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); in hw_init()
993 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); in hw_init()
1000 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, 0x00000000); in hw_init()
1001 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); in hw_init()
1004 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); in hw_init()
1005 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); in hw_init()
1006 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); in hw_init()
1007 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); in hw_init()
1008 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); in hw_init()
1009 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); in hw_init()
1010 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); in hw_init()
1011 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); in hw_init()
1012 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); in hw_init()
1013 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); in hw_init()
1014 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); in hw_init()
1015 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); in hw_init()
1018 a6xx_set_hwcg(gpu, true); in hw_init()
1023 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); in hw_init()
1024 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); in hw_init()
1025 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); in hw_init()
1026 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); in hw_init()
1027 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); in hw_init()
1028 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); in hw_init()
1030 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); in hw_init()
1034 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); in hw_init()
1037 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); in hw_init()
1040 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0); in hw_init()
1041 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff); in hw_init()
1042 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000); in hw_init()
1043 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff); in hw_init()
1044 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000); in hw_init()
1045 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff); in hw_init()
1049 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000); in hw_init()
1051 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO, in hw_init()
1055 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); in hw_init()
1056 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); in hw_init()
1060 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); in hw_init()
1062 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); in hw_init()
1063 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); in hw_init()
1066 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); in hw_init()
1069 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); in hw_init()
1075 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); in hw_init()
1077 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); in hw_init()
1079 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); in hw_init()
1081 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); in hw_init()
1084 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); in hw_init()
1087 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); in hw_init()
1090 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT); in hw_init()
1092 a6xx_set_ubwc_config(gpu); in hw_init()
1095 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, in hw_init()
1098 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); in hw_init()
1102 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); in hw_init()
1103 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, in hw_init()
1105 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, in hw_init()
1107 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, in hw_init()
1109 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, in hw_init()
1114 a6xx_set_cp_protect(gpu); in hw_init()
1117 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); in hw_init()
1118 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); in hw_init()
1123 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); in hw_init()
1126 if (gpu->hw_apriv) { in hw_init()
1127 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, in hw_init()
1132 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK); in hw_init()
1134 ret = adreno_hw_init(gpu); in hw_init()
1138 ret = a6xx_ucode_init(gpu); in hw_init()
1143 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); in hw_init()
1150 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); in hw_init()
1152 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, in hw_init()
1162 a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, in hw_init()
1163 sizeof(u32) * gpu->nr_rings, in hw_init()
1165 gpu->aspace, &a6xx_gpu->shadow_bo, in hw_init()
1174 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR_LO, in hw_init()
1175 shadowptr(a6xx_gpu, gpu->rb[0])); in hw_init()
1179 a6xx_gpu->cur_ring = gpu->rb[0]; in hw_init()
1181 gpu->cur_ctx_seqno = 0; in hw_init()
1184 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); in hw_init()
1186 ret = a6xx_cp_init(gpu); in hw_init()
1197 ret = a6xx_zap_shader_init(gpu); in hw_init()
1199 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); in hw_init()
1200 OUT_RING(gpu->rb[0], 0x00000000); in hw_init()
1202 a6xx_flush(gpu, gpu->rb[0]); in hw_init()
1203 if (!a6xx_idle(gpu, gpu->rb[0])) in hw_init()
1212 dev_warn_once(gpu->dev->dev, in hw_init()
1214 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); in hw_init()
1235 static int a6xx_hw_init(struct msm_gpu *gpu) in a6xx_hw_init() argument
1237 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_hw_init()
1242 ret = hw_init(gpu); in a6xx_hw_init()
1248 static void a6xx_dump(struct msm_gpu *gpu) in a6xx_dump() argument
1250 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", in a6xx_dump()
1251 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); in a6xx_dump()
1252 adreno_dump(gpu); in a6xx_dump()
1258 static void a6xx_recover(struct msm_gpu *gpu) in a6xx_recover() argument
1260 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_recover()
1264 adreno_dump_info(gpu); in a6xx_recover()
1267 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, in a6xx_recover()
1268 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); in a6xx_recover()
1271 a6xx_dump(gpu); in a6xx_recover()
1280 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); in a6xx_recover()
1288 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); in a6xx_recover()
1291 mutex_lock(&gpu->active_lock); in a6xx_recover()
1292 active_submits = gpu->active_submits; in a6xx_recover()
1298 gpu->active_submits = 0; in a6xx_recover()
1302 pm_runtime_put(&gpu->pdev->dev); in a6xx_recover()
1305 pm_runtime_put_sync(&gpu->pdev->dev); in a6xx_recover()
1308 reset_control_reset(gpu->cx_collapse); in a6xx_recover()
1310 pm_runtime_use_autosuspend(&gpu->pdev->dev); in a6xx_recover()
1313 pm_runtime_get(&gpu->pdev->dev); in a6xx_recover()
1315 pm_runtime_get_sync(&gpu->pdev->dev); in a6xx_recover()
1317 gpu->active_submits = active_submits; in a6xx_recover()
1318 mutex_unlock(&gpu->active_lock); in a6xx_recover()
1320 msm_gpu_hw_init(gpu); in a6xx_recover()
1324 static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) in a6xx_uche_fault_block() argument
1338 val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF); in a6xx_uche_fault_block()
1352 static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) in a6xx_fault_block() argument
1361 return a6xx_uche_fault_block(gpu, id); in a6xx_fault_block()
1370 struct msm_gpu *gpu = arg; in a6xx_fault_handler() local
1374 bool do_devcoredump = info && !READ_ONCE(gpu->crashstate); in a6xx_fault_handler()
1381 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu); in a6xx_fault_handler()
1391 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), in a6xx_fault_handler()
1392 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), in a6xx_fault_handler()
1393 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), in a6xx_fault_handler()
1394 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7))); in a6xx_fault_handler()
1406 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff); in a6xx_fault_handler()
1412 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), in a6xx_fault_handler()
1413 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), in a6xx_fault_handler()
1414 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), in a6xx_fault_handler()
1415 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7))); in a6xx_fault_handler()
1419 del_timer(&gpu->hangcheck_timer); in a6xx_fault_handler()
1421 gpu->fault_info.ttbr0 = info->ttbr0; in a6xx_fault_handler()
1422 gpu->fault_info.iova = iova; in a6xx_fault_handler()
1423 gpu->fault_info.flags = flags; in a6xx_fault_handler()
1424 gpu->fault_info.type = type; in a6xx_fault_handler()
1425 gpu->fault_info.block = block; in a6xx_fault_handler()
1427 kthread_queue_work(gpu->worker, &gpu->fault_work); in a6xx_fault_handler()
1433 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) in a6xx_cp_hw_err_irq() argument
1435 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); in a6xx_cp_hw_err_irq()
1440 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); in a6xx_cp_hw_err_irq()
1441 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); in a6xx_cp_hw_err_irq()
1442 dev_err_ratelimited(&gpu->pdev->dev, in a6xx_cp_hw_err_irq()
1448 dev_err_ratelimited(&gpu->pdev->dev, in a6xx_cp_hw_err_irq()
1452 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", in a6xx_cp_hw_err_irq()
1453 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); in a6xx_cp_hw_err_irq()
1456 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); in a6xx_cp_hw_err_irq()
1458 dev_err_ratelimited(&gpu->pdev->dev, in a6xx_cp_hw_err_irq()
1465 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); in a6xx_cp_hw_err_irq()
1468 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); in a6xx_cp_hw_err_irq()
1471 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); in a6xx_cp_hw_err_irq()
1475 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) in a6xx_fault_detect_irq() argument
1477 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_fault_detect_irq()
1479 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); in a6xx_fault_detect_irq()
1487 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT) in a6xx_fault_detect_irq()
1496 DRM_DEV_ERROR(&gpu->pdev->dev, in a6xx_fault_detect_irq()
1499 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_fault_detect_irq()
1500 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_fault_detect_irq()
1501 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), in a6xx_fault_detect_irq()
1502 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), in a6xx_fault_detect_irq()
1503 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), in a6xx_fault_detect_irq()
1504 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), in a6xx_fault_detect_irq()
1505 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); in a6xx_fault_detect_irq()
1508 del_timer(&gpu->hangcheck_timer); in a6xx_fault_detect_irq()
1510 kthread_queue_work(gpu->worker, &gpu->recover_work); in a6xx_fault_detect_irq()
1513 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) in a6xx_irq() argument
1515 struct msm_drm_private *priv = gpu->dev->dev_private; in a6xx_irq()
1516 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); in a6xx_irq()
1518 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); in a6xx_irq()
1524 a6xx_fault_detect_irq(gpu); in a6xx_irq()
1527 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); in a6xx_irq()
1530 a6xx_cp_hw_err_irq(gpu); in a6xx_irq()
1533 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); in a6xx_irq()
1536 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); in a6xx_irq()
1539 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); in a6xx_irq()
1542 msm_gpu_retire(gpu); in a6xx_irq()
1566 struct msm_gpu *gpu = &adreno_gpu->base; in a6xx_llc_activate() local
1583 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) | in a6xx_llc_activate()
1620 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval); in a6xx_llc_activate()
1655 static int a6xx_pm_resume(struct msm_gpu *gpu) in a6xx_pm_resume() argument
1657 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_pm_resume()
1661 gpu->needs_hw_init = true; in a6xx_pm_resume()
1671 msm_devfreq_resume(gpu); in a6xx_pm_resume()
1678 static int a6xx_pm_suspend(struct msm_gpu *gpu) in a6xx_pm_suspend() argument
1680 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_pm_suspend()
1688 msm_devfreq_suspend(gpu); in a6xx_pm_suspend()
1697 for (i = 0; i < gpu->nr_rings; i++) in a6xx_pm_suspend()
1700 gpu->suspend_count++; in a6xx_pm_suspend()
1705 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) in a6xx_get_timestamp() argument
1707 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_get_timestamp()
1715 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO); in a6xx_get_timestamp()
1724 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) in a6xx_active_ring() argument
1726 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_active_ring()
1732 static void a6xx_destroy(struct msm_gpu *gpu) in a6xx_destroy() argument
1734 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_destroy()
1738 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); in a6xx_destroy()
1743 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace); in a6xx_destroy()
1758 static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) in a6xx_gpu_busy() argument
1760 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gpu_busy()
1774 static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, in a6xx_gpu_set_freq() argument
1777 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gpu_set_freq()
1781 a6xx_gmu_set_freq(gpu, opp, suspended); in a6xx_gpu_set_freq()
1786 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) in a6xx_create_address_space() argument
1788 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_create_address_space()
1799 return adreno_iommu_create_address_space(gpu, pdev, quirks); in a6xx_create_address_space()
1803 a6xx_create_private_address_space(struct msm_gpu *gpu) in a6xx_create_private_address_space() argument
1807 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); in a6xx_create_private_address_space()
1814 adreno_private_address_space_size(gpu)); in a6xx_create_private_address_space()
1817 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_get_rptr() argument
1819 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_get_rptr()
1825 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); in a6xx_get_rptr()
1828 static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_progress() argument
1831 .ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), in a6xx_progress()
1832 .ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), in a6xx_progress()
1833 .ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), in a6xx_progress()
1834 .ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE), in a6xx_progress()
1851 cp_state.ib1_rem += gpu_read(gpu, REG_A6XX_CP_CSQ_IB1_STAT) >> 16; in a6xx_progress()
1852 cp_state.ib2_rem += gpu_read(gpu, REG_A6XX_CP_CSQ_IB2_STAT) >> 16; in a6xx_progress()
1991 struct msm_gpu *gpu; in a6xx_gpu_init() local
1999 gpu = &adreno_gpu->base; in a6xx_gpu_init()
2048 if (gpu->aspace) in a6xx_gpu_init()
2049 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, in a6xx_gpu_init()
2052 return gpu; in a6xx_gpu_init()