Lines Matching refs:gpu
30 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt() argument
33 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt()
85 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev); in zap_shader_load_mdt()
90 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); in zap_shader_load_mdt()
140 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) { in zap_shader_load_mdt()
176 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) in adreno_zap_shader_load() argument
178 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_zap_shader_load()
179 struct platform_device *pdev = gpu->pdev; in adreno_zap_shader_load()
191 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); in adreno_zap_shader_load()
195 adreno_create_address_space(struct msm_gpu *gpu, in adreno_create_address_space() argument
198 return adreno_iommu_create_address_space(gpu, pdev, 0); in adreno_create_address_space()
202 adreno_iommu_create_address_space(struct msm_gpu *gpu, in adreno_iommu_create_address_space() argument
236 u64 adreno_private_address_space_size(struct msm_gpu *gpu) in adreno_private_address_space_size() argument
238 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_private_address_space_size()
249 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, in adreno_get_param() argument
252 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_get_param()
283 pm_runtime_get_sync(&gpu->pdev->dev); in adreno_get_param()
284 ret = adreno_gpu->funcs->get_timestamp(gpu, value); in adreno_get_param()
285 pm_runtime_put_autosuspend(&gpu->pdev->dev); in adreno_get_param()
291 *value = gpu->nr_rings * NR_SCHED_PRIORITIES; in adreno_get_param()
298 *value = gpu->global_faults + ctx->aspace->faults; in adreno_get_param()
300 *value = gpu->global_faults; in adreno_get_param()
303 *value = gpu->suspend_count; in adreno_get_param()
306 if (ctx->aspace == gpu->aspace) in adreno_get_param()
311 if (ctx->aspace == gpu->aspace) in adreno_get_param()
316 DBG("%s: invalid param: %u", gpu->name, param); in adreno_get_param()
321 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx, in adreno_set_param() argument
355 mutex_lock(&gpu->lock); in adreno_set_param()
366 mutex_unlock(&gpu->lock); in adreno_set_param()
373 return msm_file_private_set_sysprof(ctx, gpu, value); in adreno_set_param()
375 DBG("%s: invalid param: %u", gpu->name, param); in adreno_set_param()
485 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, in adreno_fw_create_bo() argument
491 ptr = msm_gem_kernel_new(gpu->dev, fw->size - 4, in adreno_fw_create_bo()
492 MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); in adreno_fw_create_bo()
504 int adreno_hw_init(struct msm_gpu *gpu) in adreno_hw_init() argument
506 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_hw_init()
509 VERB("%s", gpu->name); in adreno_hw_init()
515 for (i = 0; i < gpu->nr_rings; i++) { in adreno_hw_init()
516 struct msm_ringbuffer *ring = gpu->rb[i]; in adreno_hw_init()
541 struct msm_gpu *gpu = &adreno_gpu->base; in get_rptr() local
543 return gpu->funcs->get_rptr(gpu, ring); in get_rptr()
546 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu) in adreno_active_ring() argument
548 return gpu->rb[0]; in adreno_active_ring()
551 void adreno_recover(struct msm_gpu *gpu) in adreno_recover() argument
553 struct drm_device *dev = gpu->dev; in adreno_recover()
559 gpu->funcs->pm_suspend(gpu); in adreno_recover()
560 gpu->funcs->pm_resume(gpu); in adreno_recover()
562 ret = msm_gpu_hw_init(gpu); in adreno_recover()
569 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg) in adreno_flush() argument
586 gpu_write(gpu, reg, wptr); in adreno_flush()
589 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in adreno_idle() argument
591 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_idle()
600 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); in adreno_idle()
605 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) in adreno_gpu_state_get() argument
607 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_gpu_state_get()
610 WARN_ON(!mutex_is_locked(&gpu->lock)); in adreno_gpu_state_get()
616 for (i = 0; i < gpu->nr_rings; i++) { in adreno_gpu_state_get()
619 state->ring[i].fence = gpu->rb[i]->memptrs->fence; in adreno_gpu_state_get()
620 state->ring[i].iova = gpu->rb[i]->iova; in adreno_gpu_state_get()
621 state->ring[i].seqno = gpu->rb[i]->fctx->last_fence; in adreno_gpu_state_get()
622 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); in adreno_gpu_state_get()
623 state->ring[i].wptr = get_wptr(gpu->rb[i]); in adreno_gpu_state_get()
630 if (gpu->rb[i]->start[j]) in adreno_gpu_state_get()
636 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2); in adreno_gpu_state_get()
662 state->registers[pos++] = gpu_read(gpu, addr); in adreno_gpu_state_get()
784 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, in adreno_show() argument
787 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_show()
817 for (i = 0; i < gpu->nr_rings; i++) { in adreno_show()
862 void adreno_dump_info(struct msm_gpu *gpu) in adreno_dump_info() argument
864 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_dump_info()
872 for (i = 0; i < gpu->nr_rings; i++) { in adreno_dump_info()
873 struct msm_ringbuffer *ring = gpu->rb[i]; in adreno_dump_info()
885 void adreno_dump(struct msm_gpu *gpu) in adreno_dump() argument
887 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_dump()
894 printk("IO:region %s 00000000 00020000\n", gpu->name); in adreno_dump()
901 uint32_t val = gpu_read(gpu, addr); in adreno_dump()
909 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu); in ring_freewords()
920 DRM_DEV_ERROR(ring->gpu->dev->dev, in adreno_wait_ring()
958 struct msm_gpu *gpu) in adreno_get_pwrlevels() argument
964 gpu->fast_rate = 0; in adreno_get_pwrlevels()
979 gpu->fast_rate = freq; in adreno_get_pwrlevels()
984 if (!gpu->fast_rate) { in adreno_get_pwrlevels()
988 gpu->fast_rate = 200000000; in adreno_get_pwrlevels()
991 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); in adreno_get_pwrlevels()
1045 struct msm_gpu *gpu = &adreno_gpu->base; in adreno_gpu_init() local
1073 adreno_get_pwrlevels(dev, gpu); in adreno_gpu_init()
1085 struct msm_gpu *gpu = &adreno_gpu->base; in adreno_gpu_cleanup() local
1086 struct msm_drm_private *priv = gpu->dev ? gpu->dev->dev_private : NULL; in adreno_gpu_cleanup()