Lines Matching refs:i0
326 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } in REG_MDP4_OVLP() argument
328 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CFG() argument
330 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } in REG_MDP4_OVLP_SIZE() argument
344 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } in REG_MDP4_OVLP_BASE() argument
346 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } in REG_MDP4_OVLP_STRIDE() argument
348 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } in REG_MDP4_OVLP_OPMODE() argument
360 …tic inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE() argument
362 … inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE_OP() argument
382 …e uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_O… in REG_MDP4_OVLP_STAGE_FG_ALPHA() argument
384 …e uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_O… in REG_MDP4_OVLP_STAGE_BG_ALPHA() argument
386 …int32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_O… in REG_MDP4_OVLP_STAGE_TRANSP_LOW0() argument
388 …int32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_O… in REG_MDP4_OVLP_STAGE_TRANSP_LOW1() argument
390 …nt32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_O… in REG_MDP4_OVLP_STAGE_TRANSP_HIGH0() argument
392 …nt32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_O… in REG_MDP4_OVLP_STAGE_TRANSP_HIGH1() argument
404 …inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE_CO3() argument
406 …ne uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_O… in REG_MDP4_OVLP_STAGE_CO3_SEL() argument
409 …tic inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0)… in REG_MDP4_OVLP_TRANSP_LOW0() argument
411 …tic inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0)… in REG_MDP4_OVLP_TRANSP_LOW1() argument
413 …ic inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0)… in REG_MDP4_OVLP_TRANSP_HIGH0() argument
415 …ic inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0)… in REG_MDP4_OVLP_TRANSP_HIGH1() argument
417 static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0… in REG_MDP4_OVLP_CSC_CONFIG() argument
419 static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CSC() argument
422 …ic inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_O… in REG_MDP4_OVLP_CSC_MV() argument
424 …nline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_O… in REG_MDP4_OVLP_CSC_MV_VAL() argument
426 …nline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_O… in REG_MDP4_OVLP_CSC_PRE_BV() argument
428 …e uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_O… in REG_MDP4_OVLP_CSC_PRE_BV_VAL() argument
430 …line uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_O… in REG_MDP4_OVLP_CSC_POST_BV() argument
432 … uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_O… in REG_MDP4_OVLP_CSC_POST_BV_VAL() argument
434 …nline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_O… in REG_MDP4_OVLP_CSC_PRE_LV() argument
436 …e uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_O… in REG_MDP4_OVLP_CSC_PRE_LV_VAL() argument
438 …line uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_O… in REG_MDP4_OVLP_CSC_POST_LV() argument
440 … uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_O… in REG_MDP4_OVLP_CSC_POST_LV_VAL() argument
444 static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; } in REG_MDP4_LUTN() argument
446 static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 +… in REG_MDP4_LUTN_LUT() argument
448 …tatic inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*… in REG_MDP4_LUTN_LUT_VAL() argument
452 static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; } in REG_MDP4_DMA_E_QUANT() argument
463 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } in REG_MDP4_DMA() argument
465 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0)… in REG_MDP4_DMA_CONFIG() argument
494 …tic inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0)… in REG_MDP4_DMA_SRC_SIZE() argument
508 …tic inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0)… in REG_MDP4_DMA_SRC_BASE() argument
510 …c inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0)… in REG_MDP4_DMA_SRC_STRIDE() argument
512 …tic inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0)… in REG_MDP4_DMA_DST_SIZE() argument
526 … inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0)… in REG_MDP4_DMA_CURSOR_SIZE() argument
540 … inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0)… in REG_MDP4_DMA_CURSOR_BASE() argument
542 …c inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0)… in REG_MDP4_DMA_CURSOR_POS() argument
556 …uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0)… in REG_MDP4_DMA_CURSOR_BLEND_CONFIG() argument
566 … uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0)… in REG_MDP4_DMA_CURSOR_BLEND_PARAM() argument
568 …ine uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0)… in REG_MDP4_DMA_BLEND_TRANS_LOW() argument
570 …ne uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0)… in REG_MDP4_DMA_BLEND_TRANS_HIGH() argument
572 …inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0)… in REG_MDP4_DMA_FETCH_CONFIG() argument
574 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); } in REG_MDP4_DMA_CSC() argument
577 …nline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_D… in REG_MDP4_DMA_CSC_MV() argument
579 …e uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_D… in REG_MDP4_DMA_CSC_MV_VAL() argument
581 …e uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_D… in REG_MDP4_DMA_CSC_PRE_BV() argument
583 …nt32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_D… in REG_MDP4_DMA_CSC_PRE_BV_VAL() argument
585 … uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_D… in REG_MDP4_DMA_CSC_POST_BV() argument
587 …t32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_D… in REG_MDP4_DMA_CSC_POST_BV_VAL() argument
589 …e uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_D… in REG_MDP4_DMA_CSC_PRE_LV() argument
591 …nt32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_D… in REG_MDP4_DMA_CSC_PRE_LV_VAL() argument
593 … uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_D… in REG_MDP4_DMA_CSC_POST_LV() argument
595 …t32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_D… in REG_MDP4_DMA_CSC_POST_LV_VAL() argument
597 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } in REG_MDP4_PIPE() argument
599 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } in REG_MDP4_PIPE_SRC_SIZE() argument
613 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; } in REG_MDP4_PIPE_SRC_XY() argument
627 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; } in REG_MDP4_PIPE_DST_SIZE() argument
641 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; } in REG_MDP4_PIPE_DST_XY() argument
655 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0… in REG_MDP4_PIPE_SRCP0_BASE() argument
657 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0… in REG_MDP4_PIPE_SRCP1_BASE() argument
659 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0… in REG_MDP4_PIPE_SRCP2_BASE() argument
661 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0… in REG_MDP4_PIPE_SRCP3_BASE() argument
663 …c inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; } in REG_MDP4_PIPE_SRC_STRIDE_A() argument
677 …c inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; } in REG_MDP4_PIPE_SRC_STRIDE_B() argument
691 …ine uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } in REG_MDP4_PIPE_SSTILE_FRAME_SIZE() argument
705 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0… in REG_MDP4_PIPE_SRC_FORMAT() argument
766 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0… in REG_MDP4_PIPE_SRC_UNPACK() argument
792 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; } in REG_MDP4_PIPE_OP_MODE() argument
817 …ic inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; } in REG_MDP4_PIPE_PHASEX_STEP() argument
819 …ic inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; } in REG_MDP4_PIPE_PHASEY_STEP() argument
821 …c inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; } in REG_MDP4_PIPE_FETCH_CONFIG() argument
823 …ic inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; } in REG_MDP4_PIPE_SOLID_COLOR() argument
825 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; } in REG_MDP4_PIPE_CSC() argument
828 …inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000… in REG_MDP4_PIPE_CSC_MV() argument
830 …ne uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000… in REG_MDP4_PIPE_CSC_MV_VAL() argument
832 …ne uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000… in REG_MDP4_PIPE_CSC_PRE_BV() argument
834 …int32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000… in REG_MDP4_PIPE_CSC_PRE_BV_VAL() argument
836 …e uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000… in REG_MDP4_PIPE_CSC_POST_BV() argument
838 …nt32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000… in REG_MDP4_PIPE_CSC_POST_BV_VAL() argument
840 …ne uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000… in REG_MDP4_PIPE_CSC_PRE_LV() argument
842 …int32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000… in REG_MDP4_PIPE_CSC_PRE_LV_VAL() argument
844 …e uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000… in REG_MDP4_PIPE_CSC_POST_LV() argument
846 …nt32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000… in REG_MDP4_PIPE_CSC_POST_LV_VAL() argument
945 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; } in REG_MDP4_LCDC_LVDS_MUX_CTL() argument
947 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0;… in REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0() argument
973 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0;… in REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4() argument