Lines Matching refs:i0
276 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W() argument
278 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W_REG() argument
298 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R() argument
300 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R_REG() argument
330 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } in REG_MDP5_IGC() argument
332 …ine uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_I… in REG_MDP5_IGC_LUT() argument
334 …uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_I… in REG_MDP5_IGC_LUT_REG() argument
371 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); } in REG_MDP5_CTL() argument
385 …atic inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER() argument
387 … inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER_REG() argument
451 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); } in REG_MDP5_CTL_OP() argument
473 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); } in REG_MDP5_CTL_FLUSH() argument
504 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); } in REG_MDP5_CTL_START() argument
506 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); } in REG_MDP5_CTL_PACK_3D() argument
520 … inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER_EXT() argument
522 …ine uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_C… in REG_MDP5_CTL_LAYER_EXT_REG() argument
565 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); } in REG_MDP5_PIPE() argument
567 …c inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0)… in REG_MDP5_PIPE_OP_MODE() argument
582 …ne uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0)… in REG_MDP5_PIPE_HIST_CTL_BASE() argument
584 …ne uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0)… in REG_MDP5_PIPE_HIST_LUT_BASE() argument
586 …ne uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0)… in REG_MDP5_PIPE_HIST_LUT_SWAP() argument
588 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0() argument
602 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1() argument
616 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2() argument
630 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3() argument
644 …32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4() argument
652 …2_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_P… in REG_MDP5_PIPE_CSC_1_PRE_CLAMP() argument
654 …REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_P… in REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG() argument
668 …_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_P… in REG_MDP5_PIPE_CSC_1_POST_CLAMP() argument
670 …EG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_P… in REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG() argument
684 …32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_P… in REG_MDP5_PIPE_CSC_1_PRE_BIAS() argument
686 … REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_P… in REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG() argument
694 …2_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_P… in REG_MDP5_PIPE_CSC_1_POST_BIAS() argument
696 …REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_P… in REG_MDP5_PIPE_CSC_1_POST_BIAS_REG() argument
704 … inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_SIZE() argument
718 …ine uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_IMG_SIZE() argument
732 …ic inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_XY() argument
746 … inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0)… in REG_MDP5_PIPE_OUT_SIZE() argument
760 …ic inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0)… in REG_MDP5_PIPE_OUT_XY() argument
774 …inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC0_ADDR() argument
776 …inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC1_ADDR() argument
778 …inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC2_ADDR() argument
780 …inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC3_ADDR() argument
782 …ine uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_STRIDE_A() argument
796 …ine uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_STRIDE_B() argument
810 …uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0)… in REG_MDP5_PIPE_STILE_FRAME_SIZE() argument
812 …nline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_FORMAT() argument
866 …nline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_UNPACK() argument
892 …line uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_OP_MODE() argument
909 …nt32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_CONSTANT_COLOR() argument
911 …ine uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0)… in REG_MDP5_PIPE_FETCH_CONFIG() argument
913 …inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0)… in REG_MDP5_PIPE_VC1_RANGE() argument
915 …int32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0)… in REG_MDP5_PIPE_REQPRIO_FIFO_WM_0() argument
917 …int32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0)… in REG_MDP5_PIPE_REQPRIO_FIFO_WM_1() argument
919 …int32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0)… in REG_MDP5_PIPE_REQPRIO_FIFO_WM_2() argument
921 …nt32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SRC_ADDR_SW_STATUS() argument
923 …int32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CURRENT_SRC0_ADDR() argument
925 …int32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CURRENT_SRC1_ADDR() argument
927 …int32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0)… in REG_MDP5_PIPE_CURRENT_SRC2_ADDR() argument
929 …int32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0)… in REG_MDP5_PIPE_CURRENT_SRC3_ADDR() argument
931 …nline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0)… in REG_MDP5_PIPE_DECIMATION() argument
954 … REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __o… in REG_MDP5_PIPE_SW_PIX_EXT() argument
956 …G_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __o… in REG_MDP5_PIPE_SW_PIX_EXT_LR() argument
982 …G_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __o… in REG_MDP5_PIPE_SW_PIX_EXT_TB() argument
1008 …IPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __o… in REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS() argument
1022 …ine uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_CONFIG() argument
1062 …nt32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_PHASE_STEP_X() argument
1064 …nt32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_PHASE_STEP_Y() argument
1066 …2_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X() argument
1068 …2_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y() argument
1070 …nt32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_INIT_PHASE_X() argument
1072 …nt32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0)… in REG_MDP5_PIPE_SCALE_INIT_PHASE_Y() argument
1086 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); } in REG_MDP5_LM() argument
1088 …ic inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0);… in REG_MDP5_LM_BLEND_COLOR_OUT() argument
1098 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); } in REG_MDP5_LM_OUT_SIZE() argument
1112 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0… in REG_MDP5_LM_BORDER_COLOR_0() argument
1114 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0… in REG_MDP5_LM_BORDER_COLOR_1() argument
1129 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_L… in REG_MDP5_LM_BLEND() argument
1131 …nline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_… in REG_MDP5_LM_BLEND_OP_MODE() argument
1153 …line uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_… in REG_MDP5_LM_BLEND_FG_ALPHA() argument
1155 …line uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_… in REG_MDP5_LM_BLEND_BG_ALPHA() argument
1157 …int32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_… in REG_MDP5_LM_BLEND_FG_TRANSP_LOW0() argument
1159 …int32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_… in REG_MDP5_LM_BLEND_FG_TRANSP_LOW1() argument
1161 …nt32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_… in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0() argument
1163 …nt32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_… in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1() argument
1165 …int32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_… in REG_MDP5_LM_BLEND_BG_TRANSP_LOW0() argument
1167 …int32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_… in REG_MDP5_LM_BLEND_BG_TRANSP_LOW1() argument
1169 …nt32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_… in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0() argument
1171 …nt32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_… in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1() argument
1173 …ic inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_IMG_SIZE() argument
1187 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); } in REG_MDP5_LM_CURSOR_SIZE() argument
1201 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); } in REG_MDP5_LM_CURSOR_XY() argument
1215 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0)… in REG_MDP5_LM_CURSOR_STRIDE() argument
1223 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0)… in REG_MDP5_LM_CURSOR_FORMAT() argument
1231 …c inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BASE_ADDR() argument
1233 …ic inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_START_XY() argument
1247 …nline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_CONFIG() argument
1257 …inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_PARAM() argument
1259 … uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0() argument
1261 … uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1() argument
1263 …uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0() argument
1265 …uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0);… in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1() argument
1267 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); } in REG_MDP5_LM_GC_LUT_BASE() argument
1279 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } in REG_MDP5_DSPP() argument
1281 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } in REG_MDP5_DSPP_OP_MODE() argument
1298 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0);… in REG_MDP5_DSPP_PCC_BASE() argument
1300 …ic inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0)… in REG_MDP5_DSPP_DITHER_DEPTH() argument
1302 …c inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0)… in REG_MDP5_DSPP_HIST_CTL_BASE() argument
1304 …c inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0)… in REG_MDP5_DSPP_HIST_LUT_BASE() argument
1306 …c inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0)… in REG_MDP5_DSPP_HIST_LUT_SWAP() argument
1308 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); } in REG_MDP5_DSPP_PA_BASE() argument
1310 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0… in REG_MDP5_DSPP_GAMUT_BASE() argument
1312 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); } in REG_MDP5_DSPP_GC_BASE() argument
1324 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); } in REG_MDP5_PP() argument
1326 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0)… in REG_MDP5_PP_TEAR_CHECK_EN() argument
1328 … inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0);… in REG_MDP5_PP_SYNC_CONFIG_VSYNC() argument
1338 …inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0);… in REG_MDP5_PP_SYNC_CONFIG_HEIGHT() argument
1340 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0);… in REG_MDP5_PP_SYNC_WRCOUNT() argument
1354 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0… in REG_MDP5_PP_VSYNC_INIT_VAL() argument
1356 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0)… in REG_MDP5_PP_INT_COUNT_VAL() argument
1370 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); } in REG_MDP5_PP_SYNC_THRESH() argument
1384 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); } in REG_MDP5_PP_START_POS() argument
1386 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); } in REG_MDP5_PP_RD_PTR_IRQ() argument
1388 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); } in REG_MDP5_PP_WR_PTR_IRQ() argument
1390 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0… in REG_MDP5_PP_OUT_LINE_COUNT() argument
1392 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0)… in REG_MDP5_PP_PP_LINE_COUNT() argument
1394 …inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0);… in REG_MDP5_PP_AUTOREFRESH_CONFIG() argument
1396 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); } in REG_MDP5_PP_FBC_MODE() argument
1398 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0… in REG_MDP5_PP_FBC_BUDGET_CTL() argument
1400 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0… in REG_MDP5_PP_FBC_LOSSY_MODE() argument
1415 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } in REG_MDP5_WB() argument
1417 static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } in REG_MDP5_WB_DST_FORMAT() argument
1484 static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); } in REG_MDP5_WB_DST_OP_MODE() argument
1538 …c inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0);… in REG_MDP5_WB_DST_PACK_PATTERN() argument
1564 static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); } in REG_MDP5_WB_DST0_ADDR() argument
1566 static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); } in REG_MDP5_WB_DST1_ADDR() argument
1568 static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); } in REG_MDP5_WB_DST2_ADDR() argument
1570 static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); } in REG_MDP5_WB_DST3_ADDR() argument
1572 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0);… in REG_MDP5_WB_DST_YSTRIDE0() argument
1586 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0);… in REG_MDP5_WB_DST_YSTRIDE1() argument
1600 …nline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0);… in REG_MDP5_WB_DST_DITHER_BITDEPTH() argument
1602 …inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0);… in REG_MDP5_WB_DITHER_MATRIX_ROW0() argument
1604 …inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0);… in REG_MDP5_WB_DITHER_MATRIX_ROW1() argument
1606 …inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0);… in REG_MDP5_WB_DITHER_MATRIX_ROW2() argument
1608 …inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0);… in REG_MDP5_WB_DITHER_MATRIX_ROW3() argument
1610 …c inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0);… in REG_MDP5_WB_DST_WRITE_CONFIG() argument
1612 … inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0);… in REG_MDP5_WB_ROTATION_DNSCALER() argument
1614 …line uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0);… in REG_MDP5_WB_N16_INIT_PHASE_X_0_3() argument
1616 …line uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0);… in REG_MDP5_WB_N16_INIT_PHASE_X_1_2() argument
1618 …line uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0);… in REG_MDP5_WB_N16_INIT_PHASE_Y_0_3() argument
1620 …line uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0);… in REG_MDP5_WB_N16_INIT_PHASE_Y_1_2() argument
1622 static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); } in REG_MDP5_WB_OUT_SIZE() argument
1636 static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0)… in REG_MDP5_WB_ALPHA_X_VALUE() argument
1638 …inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0);… in REG_MDP5_WB_CSC_MATRIX_COEFF_0() argument
1652 …inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0);… in REG_MDP5_WB_CSC_MATRIX_COEFF_1() argument
1666 …inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0);… in REG_MDP5_WB_CSC_MATRIX_COEFF_2() argument
1680 …inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0);… in REG_MDP5_WB_CSC_MATRIX_COEFF_3() argument
1694 …inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0);… in REG_MDP5_WB_CSC_MATRIX_COEFF_4() argument
1702 …e uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_… in REG_MDP5_WB_CSC_COMP_PRECLAMP() argument
1704 …nt32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_… in REG_MDP5_WB_CSC_COMP_PRECLAMP_REG() argument
1718 … uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_… in REG_MDP5_WB_CSC_COMP_POSTCLAMP() argument
1720 …t32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_… in REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG() argument
1734 …ne uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_… in REG_MDP5_WB_CSC_COMP_PREBIAS() argument
1736 …int32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_… in REG_MDP5_WB_CSC_COMP_PREBIAS_REG() argument
1744 …e uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_… in REG_MDP5_WB_CSC_COMP_POSTBIAS() argument
1746 …nt32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_… in REG_MDP5_WB_CSC_COMP_POSTBIAS_REG() argument
1765 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } in REG_MDP5_INTF() argument
1767 …nline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0)… in REG_MDP5_INTF_TIMING_ENGINE_EN() argument
1769 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); } in REG_MDP5_INTF_CONFIG() argument
1771 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0)… in REG_MDP5_INTF_HSYNC_CTL() argument
1785 …inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0)… in REG_MDP5_INTF_VSYNC_PERIOD_F0() argument
1787 …inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0)… in REG_MDP5_INTF_VSYNC_PERIOD_F1() argument
1789 …ic inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0)… in REG_MDP5_INTF_VSYNC_LEN_F0() argument
1791 …ic inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0)… in REG_MDP5_INTF_VSYNC_LEN_F1() argument
1793 …line uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_VSTART_F0() argument
1795 …line uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_VSTART_F1() argument
1797 …inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_VEND_F0() argument
1799 …inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_VEND_F1() argument
1801 …nline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_VSTART_F0() argument
1810 …nline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_VSTART_F1() argument
1818 … inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_VEND_F0() argument
1820 … inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_VEND_F1() argument
1822 …ic inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0)… in REG_MDP5_INTF_DISPLAY_HCTL() argument
1836 …tic inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0)… in REG_MDP5_INTF_ACTIVE_HCTL() argument
1851 …ic inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0)… in REG_MDP5_INTF_BORDER_COLOR() argument
1853 …inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0)… in REG_MDP5_INTF_UNDERFLOW_COLOR() argument
1855 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0… in REG_MDP5_INTF_HSYNC_SKEW() argument
1857 …ic inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0)… in REG_MDP5_INTF_POLARITY_CTL() argument
1862 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0);… in REG_MDP5_INTF_TEST_CTL() argument
1864 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0)… in REG_MDP5_INTF_TP_COLOR0() argument
1866 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0)… in REG_MDP5_INTF_TP_COLOR1() argument
1868 …int32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0)… in REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN() argument
1870 …ic inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0)… in REG_MDP5_INTF_PANEL_FORMAT() argument
1872 …ne uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0)… in REG_MDP5_INTF_FRAME_LINE_COUNT_EN() argument
1874 …tic inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0)… in REG_MDP5_INTF_FRAME_COUNT() argument
1876 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0… in REG_MDP5_INTF_LINE_COUNT() argument
1878 …nline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0)… in REG_MDP5_INTF_DEFLICKER_CONFIG() argument
1880 … uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0)… in REG_MDP5_INTF_DEFLICKER_STRNG_COEFF() argument
1882 …e uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0)… in REG_MDP5_INTF_DEFLICKER_WEAK_COEFF() argument
1884 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0… in REG_MDP5_INTF_TPG_ENABLE() argument
1886 …nline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_MAIN_CONTROL() argument
1888 …nline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_VIDEO_CONFIG() argument
1890 …e uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_COMPONENT_LIMITS() argument
1892 …c inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_RECTANGLE() argument
1894 …line uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_INITIAL_VALUE() argument
1896 …2_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME() argument
1898 …inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0)… in REG_MDP5_INTF_TPG_RGB_MAPPING() argument
1908 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } in REG_MDP5_AD() argument
1910 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } in REG_MDP5_AD_BYPASS() argument
1912 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); } in REG_MDP5_AD_CTRL_0() argument
1914 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); } in REG_MDP5_AD_CTRL_1() argument
1916 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); } in REG_MDP5_AD_FRAME_SIZE() argument
1918 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); } in REG_MDP5_AD_CON_CTRL_0() argument
1920 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); } in REG_MDP5_AD_CON_CTRL_1() argument
1922 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); } in REG_MDP5_AD_STR_MAN() argument
1924 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); } in REG_MDP5_AD_VAR() argument
1926 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); } in REG_MDP5_AD_DITH() argument
1928 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); } in REG_MDP5_AD_DITH_CTRL() argument
1930 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); } in REG_MDP5_AD_AMP_LIM() argument
1932 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); } in REG_MDP5_AD_SLOPE() argument
1934 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); } in REG_MDP5_AD_BW_LVL() argument
1936 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); } in REG_MDP5_AD_LOGO_POS() argument
1938 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); } in REG_MDP5_AD_LUT_FI() argument
1940 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); } in REG_MDP5_AD_LUT_CC() argument
1942 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); } in REG_MDP5_AD_STR_LIM() argument
1944 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); } in REG_MDP5_AD_CALIB_AB() argument
1946 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); } in REG_MDP5_AD_CALIB_CD() argument
1948 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); } in REG_MDP5_AD_MODE_SEL() argument
1950 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); } in REG_MDP5_AD_TFILT_CTRL() argument
1952 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); } in REG_MDP5_AD_BL_MINMAX() argument
1954 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); } in REG_MDP5_AD_BL() argument
1956 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); } in REG_MDP5_AD_BL_MAX() argument
1958 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); } in REG_MDP5_AD_AL() argument
1960 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); } in REG_MDP5_AD_AL_MIN() argument
1962 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); } in REG_MDP5_AD_AL_FILT() argument
1964 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); } in REG_MDP5_AD_CFG_BUF() argument
1966 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); } in REG_MDP5_AD_LUT_AL() argument
1968 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); } in REG_MDP5_AD_TARG_STR() argument
1970 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); } in REG_MDP5_AD_START_CALC() argument
1972 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); } in REG_MDP5_AD_STR_OUT() argument
1974 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); } in REG_MDP5_AD_BL_OUT() argument
1976 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); } in REG_MDP5_AD_CALC_DONE() argument