Lines Matching refs:regp
398 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_save_state_ramdac() local
402 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); in nv_save_state_ramdac()
404 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); in nv_save_state_ramdac()
409 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); in nv_save_state_ramdac()
411 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); in nv_save_state_ramdac()
414 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); in nv_save_state_ramdac()
416 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); in nv_save_state_ramdac()
418 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); in nv_save_state_ramdac()
419 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); in nv_save_state_ramdac()
420 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); in nv_save_state_ramdac()
421 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); in nv_save_state_ramdac()
422 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); in nv_save_state_ramdac()
423 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); in nv_save_state_ramdac()
424 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); in nv_save_state_ramdac()
425 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); in nv_save_state_ramdac()
429 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); in nv_save_state_ramdac()
430 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); in nv_save_state_ramdac()
434 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); in nv_save_state_ramdac()
436 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); in nv_save_state_ramdac()
437 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); in nv_save_state_ramdac()
441 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); in nv_save_state_ramdac()
442 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); in nv_save_state_ramdac()
446 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 & in nv_save_state_ramdac()
449 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); in nv_save_state_ramdac()
450 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); in nv_save_state_ramdac()
452 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); in nv_save_state_ramdac()
455 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); in nv_save_state_ramdac()
458 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); in nv_save_state_ramdac()
459 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); in nv_save_state_ramdac()
460 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); in nv_save_state_ramdac()
463 regp->ctv_regs[i] = NVReadRAMDAC(dev, head, in nv_save_state_ramdac()
474 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_load_state_ramdac() local
479 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); in nv_load_state_ramdac()
481 clk->pll_prog(clk, pllreg, ®p->pllvals); in nv_load_state_ramdac()
486 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); in nv_load_state_ramdac()
488 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); in nv_load_state_ramdac()
491 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); in nv_load_state_ramdac()
493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); in nv_load_state_ramdac()
495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); in nv_load_state_ramdac()
496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); in nv_load_state_ramdac()
497 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); in nv_load_state_ramdac()
498 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); in nv_load_state_ramdac()
499 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); in nv_load_state_ramdac()
500 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); in nv_load_state_ramdac()
501 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); in nv_load_state_ramdac()
502 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); in nv_load_state_ramdac()
507 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); in nv_load_state_ramdac()
508 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); in nv_load_state_ramdac()
512 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); in nv_load_state_ramdac()
514 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); in nv_load_state_ramdac()
515 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); in nv_load_state_ramdac()
519 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); in nv_load_state_ramdac()
520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); in nv_load_state_ramdac()
521 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); in nv_load_state_ramdac()
522 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); in nv_load_state_ramdac()
524 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); in nv_load_state_ramdac()
527 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); in nv_load_state_ramdac()
530 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); in nv_load_state_ramdac()
531 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); in nv_load_state_ramdac()
532 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); in nv_load_state_ramdac()
536 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]); in nv_load_state_ramdac()
544 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_save_state_vga() local
547 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); in nv_save_state_vga()
550 rd_cio_state(dev, head, regp, i); in nv_save_state_vga()
554 regp->Attribute[i] = NVReadVgaAttr(dev, head, i); in nv_save_state_vga()
558 regp->Graphics[i] = NVReadVgaGr(dev, head, i); in nv_save_state_vga()
561 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); in nv_save_state_vga()
568 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_load_state_vga() local
571 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); in nv_load_state_vga()
574 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); in nv_load_state_vga()
578 wr_cio_state(dev, head, regp, i); in nv_load_state_vga()
582 NVWriteVgaGr(dev, head, i, regp->Graphics[i]); in nv_load_state_vga()
586 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); in nv_load_state_vga()
595 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_save_state_ext() local
598 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); in nv_save_state_ext()
599 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); in nv_save_state_ext()
600 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); in nv_save_state_ext()
601 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); in nv_save_state_ext()
602 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); in nv_save_state_ext()
603 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); in nv_save_state_ext()
604 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); in nv_save_state_ext()
606 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); in nv_save_state_ext()
607 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); in nv_save_state_ext()
608 rd_cio_state(dev, head, regp, NV_CIO_CRE_21); in nv_save_state_ext()
611 rd_cio_state(dev, head, regp, NV_CIO_CRE_47); in nv_save_state_ext()
614 rd_cio_state(dev, head, regp, 0x9f); in nv_save_state_ext()
616 rd_cio_state(dev, head, regp, NV_CIO_CRE_49); in nv_save_state_ext()
617 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); in nv_save_state_ext()
618 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); in nv_save_state_ext()
619 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); in nv_save_state_ext()
620 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); in nv_save_state_ext()
623 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); in nv_save_state_ext()
624 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); in nv_save_state_ext()
627 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); in nv_save_state_ext()
630 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); in nv_save_state_ext()
633 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); in nv_save_state_ext()
634 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); in nv_save_state_ext()
637 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); in nv_save_state_ext()
639 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); in nv_save_state_ext()
640 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); in nv_save_state_ext()
642 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); in nv_save_state_ext()
643 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); in nv_save_state_ext()
644 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); in nv_save_state_ext()
645 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); in nv_save_state_ext()
649 rd_cio_state(dev, head, regp, NV_CIO_CRE_42); in nv_save_state_ext()
650 rd_cio_state(dev, head, regp, NV_CIO_CRE_53); in nv_save_state_ext()
651 rd_cio_state(dev, head, regp, NV_CIO_CRE_54); in nv_save_state_ext()
654 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); in nv_save_state_ext()
655 rd_cio_state(dev, head, regp, NV_CIO_CRE_59); in nv_save_state_ext()
656 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); in nv_save_state_ext()
658 rd_cio_state(dev, head, regp, NV_CIO_CRE_85); in nv_save_state_ext()
659 rd_cio_state(dev, head, regp, NV_CIO_CRE_86); in nv_save_state_ext()
662 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); in nv_save_state_ext()
671 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_load_state_ext() local
681 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); in nv_load_state_ext()
693 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); in nv_load_state_ext()
694 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); in nv_load_state_ext()
695 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); in nv_load_state_ext()
698 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); in nv_load_state_ext()
701 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); in nv_load_state_ext()
704 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC) in nv_load_state_ext()
711 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); in nv_load_state_ext()
713 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); in nv_load_state_ext()
714 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); in nv_load_state_ext()
715 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); in nv_load_state_ext()
716 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); in nv_load_state_ext()
717 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); in nv_load_state_ext()
718 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); in nv_load_state_ext()
719 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); in nv_load_state_ext()
720 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); in nv_load_state_ext()
721 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); in nv_load_state_ext()
724 wr_cio_state(dev, head, regp, NV_CIO_CRE_47); in nv_load_state_ext()
727 wr_cio_state(dev, head, regp, 0x9f); in nv_load_state_ext()
729 wr_cio_state(dev, head, regp, NV_CIO_CRE_49); in nv_load_state_ext()
730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); in nv_load_state_ext()
731 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); in nv_load_state_ext()
732 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); in nv_load_state_ext()
735 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); in nv_load_state_ext()
737 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); in nv_load_state_ext()
738 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); in nv_load_state_ext()
740 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); in nv_load_state_ext()
741 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); in nv_load_state_ext()
742 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); in nv_load_state_ext()
743 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); in nv_load_state_ext()
760 wr_cio_state(dev, head, regp, NV_CIO_CRE_42); in nv_load_state_ext()
761 wr_cio_state(dev, head, regp, NV_CIO_CRE_53); in nv_load_state_ext()
762 wr_cio_state(dev, head, regp, NV_CIO_CRE_54); in nv_load_state_ext()
765 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); in nv_load_state_ext()
766 wr_cio_state(dev, head, regp, NV_CIO_CRE_59); in nv_load_state_ext()
767 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); in nv_load_state_ext()
769 wr_cio_state(dev, head, regp, NV_CIO_CRE_85); in nv_load_state_ext()
770 wr_cio_state(dev, head, regp, NV_CIO_CRE_86); in nv_load_state_ext()
773 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); in nv_load_state_ext()