Lines Matching refs:FLD_MOD
54 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
1312 r = FLD_MOD(r, lane_number + 1, offset + 2, offset); in dsi_set_lane_config()
1313 r = FLD_MOD(r, polarity, offset + 3, offset + 3); in dsi_set_lane_config()
1320 r = FLD_MOD(r, 0, offset + 2, offset); in dsi_set_lane_config()
1321 r = FLD_MOD(r, 0, offset + 3, offset + 3); in dsi_set_lane_config()
1397 r = FLD_MOD(r, ths_prepare, 31, 24); in dsi_cio_timings()
1398 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); in dsi_cio_timings()
1399 r = FLD_MOD(r, ths_trail, 15, 8); in dsi_cio_timings()
1400 r = FLD_MOD(r, ths_exit, 7, 0); in dsi_cio_timings()
1404 r = FLD_MOD(r, tlpx_half, 20, 16); in dsi_cio_timings()
1405 r = FLD_MOD(r, tclk_trail, 15, 8); in dsi_cio_timings()
1406 r = FLD_MOD(r, tclk_zero, 7, 0); in dsi_cio_timings()
1409 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ in dsi_cio_timings()
1410 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ in dsi_cio_timings()
1411 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ in dsi_cio_timings()
1417 r = FLD_MOD(r, tclk_prepare, 7, 0); in dsi_cio_timings()
1589 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ in dsi_cio_init()
1590 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ in dsi_cio_init()
1591 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ in dsi_cio_init()
1592 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ in dsi_cio_init()
1717 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ in dsi_force_tx_stop_mode_io()
1878 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ in dsi_vc_initial_config()
1879 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ in dsi_vc_initial_config()
1880 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ in dsi_vc_initial_config()
1881 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ in dsi_vc_initial_config()
1882 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ in dsi_vc_initial_config()
1883 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ in dsi_vc_initial_config()
1884 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ in dsi_vc_initial_config()
1886 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ in dsi_vc_initial_config()
1888 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ in dsi_vc_initial_config()
1889 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ in dsi_vc_initial_config()
2416 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ in dsi_set_lp_rx_timeout()
2417 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ in dsi_set_lp_rx_timeout()
2418 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ in dsi_set_lp_rx_timeout()
2419 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ in dsi_set_lp_rx_timeout()
2443 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ in dsi_set_ta_timeout()
2444 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ in dsi_set_ta_timeout()
2445 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ in dsi_set_ta_timeout()
2446 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ in dsi_set_ta_timeout()
2470 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ in dsi_set_stop_state_counter()
2471 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ in dsi_set_stop_state_counter()
2472 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ in dsi_set_stop_state_counter()
2473 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ in dsi_set_stop_state_counter()
2497 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ in dsi_set_hs_tx_timeout()
2498 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ in dsi_set_hs_tx_timeout()
2499 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ in dsi_set_hs_tx_timeout()
2500 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ in dsi_set_hs_tx_timeout()
2546 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ in dsi_config_vp_sync_events()
2547 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ in dsi_config_vp_sync_events()
2548 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ in dsi_config_vp_sync_events()
2549 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ in dsi_config_vp_sync_events()
2550 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ in dsi_config_vp_sync_events()
2551 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ in dsi_config_vp_sync_events()
2552 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ in dsi_config_vp_sync_events()
2569 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ in dsi_config_blanking_modes()
2570 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ in dsi_config_blanking_modes()
2571 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ in dsi_config_blanking_modes()
2572 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ in dsi_config_blanking_modes()
2737 r = FLD_MOD(r, hsa_interleave_hs, 23, 16); in dsi_config_cmd_mode_interleaving()
2738 r = FLD_MOD(r, hfp_interleave_hs, 15, 8); in dsi_config_cmd_mode_interleaving()
2739 r = FLD_MOD(r, hbp_interleave_hs, 7, 0); in dsi_config_cmd_mode_interleaving()
2743 r = FLD_MOD(r, hsa_interleave_lp, 23, 16); in dsi_config_cmd_mode_interleaving()
2744 r = FLD_MOD(r, hfp_interleave_lp, 15, 8); in dsi_config_cmd_mode_interleaving()
2745 r = FLD_MOD(r, hbp_interleave_lp, 7, 0); in dsi_config_cmd_mode_interleaving()
2749 r = FLD_MOD(r, bl_interleave_hs, 31, 15); in dsi_config_cmd_mode_interleaving()
2750 r = FLD_MOD(r, bl_interleave_lp, 16, 0); in dsi_config_cmd_mode_interleaving()
2791 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ in dsi_proto_config()
2792 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ in dsi_proto_config()
2793 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ in dsi_proto_config()
2794 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ in dsi_proto_config()
2795 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ in dsi_proto_config()
2796 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ in dsi_proto_config()
2797 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ in dsi_proto_config()
2798 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ in dsi_proto_config()
2800 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ in dsi_proto_config()
2802 r = FLD_MOD(r, 0, 25, 25); in dsi_proto_config()
2864 r = FLD_MOD(r, ddr_clk_pre, 15, 8); in dsi_proto_timings()
2865 r = FLD_MOD(r, ddr_clk_post, 7, 0); in dsi_proto_timings()
2915 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ in dsi_proto_timings()
2916 r = FLD_MOD(r, hfp, 23, 12); /* HFP */ in dsi_proto_timings()
2917 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ in dsi_proto_timings()
2921 r = FLD_MOD(r, vbp, 7, 0); /* VBP */ in dsi_proto_timings()
2922 r = FLD_MOD(r, vfp, 15, 8); /* VFP */ in dsi_proto_timings()
2923 r = FLD_MOD(r, vsa, 23, 16); /* VSA */ in dsi_proto_timings()
2924 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ in dsi_proto_timings()
2928 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */ in dsi_proto_timings()
2929 r = FLD_MOD(r, tl, 31, 16); /* TL */ in dsi_proto_timings()
3134 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ in dsi_update_screen_dispc()
3136 l = FLD_MOD(l, 1, 31, 31); /* TE_START */ in dsi_update_screen_dispc()