Lines Matching refs:radeon_crtc
44 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_overscan_setup() local
51 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
53 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
74 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
75 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
76 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
77 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
87 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_scaler_setup() local
91 to_radeon_encoder(radeon_crtc->encoder); in atombios_scaler_setup()
96 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) in atombios_scaler_setup()
107 args.ucScaler = radeon_crtc->crtc_id; in atombios_scaler_setup()
142 switch (radeon_crtc->rmx_type) { in atombios_scaler_setup()
163 atom_rv515_force_tv_scaler(rdev, radeon_crtc); in atombios_scaler_setup()
169 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_lock_crtc() local
178 args.ucCRTC = radeon_crtc->crtc_id; in atombios_lock_crtc()
186 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_enable_crtc() local
194 args.ucCRTC = radeon_crtc->crtc_id; in atombios_enable_crtc()
202 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_enable_crtc_memreq() local
210 args.ucCRTC = radeon_crtc->crtc_id; in atombios_enable_crtc_memreq()
228 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_blank_crtc() local
238 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); in atombios_blank_crtc()
239 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); in atombios_blank_crtc()
242 args.ucCRTC = radeon_crtc->crtc_id; in atombios_blank_crtc()
248 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); in atombios_blank_crtc()
253 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_powergate_crtc() local
261 args.ucDispPipeId = radeon_crtc->crtc_id; in atombios_powergate_crtc()
271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_dpms() local
275 radeon_crtc->enabled = true; in atombios_crtc_dpms()
280 if (dev->num_crtcs > radeon_crtc->crtc_id) in atombios_crtc_dpms()
287 if (dev->num_crtcs > radeon_crtc->crtc_id) in atombios_crtc_dpms()
289 if (radeon_crtc->enabled) in atombios_crtc_dpms()
294 radeon_crtc->enabled = false; in atombios_crtc_dpms()
305 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_set_crtc_dtd_timing() local
313 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing()
315 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing()
316 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); in atombios_set_crtc_dtd_timing()
318 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); in atombios_set_crtc_dtd_timing()
320 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); in atombios_set_crtc_dtd_timing()
324 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); in atombios_set_crtc_dtd_timing()
327 args.ucH_Border = radeon_crtc->h_border; in atombios_set_crtc_dtd_timing()
328 args.ucV_Border = radeon_crtc->v_border; in atombios_set_crtc_dtd_timing()
344 args.ucCRTC = radeon_crtc->crtc_id; in atombios_set_crtc_dtd_timing()
352 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_set_timing() local
371 args.ucOverscanRight = radeon_crtc->h_border; in atombios_crtc_set_timing()
372 args.ucOverscanLeft = radeon_crtc->h_border; in atombios_crtc_set_timing()
373 args.ucOverscanBottom = radeon_crtc->v_border; in atombios_crtc_set_timing()
374 args.ucOverscanTop = radeon_crtc->v_border; in atombios_crtc_set_timing()
390 args.ucCRTC = radeon_crtc->crtc_id; in atombios_crtc_set_timing()
560 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_adjust_pll() local
563 struct drm_encoder *encoder = radeon_crtc->encoder; in atombios_adjust_pll()
570 int bpc = radeon_crtc->bpc; in atombios_adjust_pll()
574 radeon_crtc->pll_flags = 0; in atombios_adjust_pll()
580 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ in atombios_adjust_pll()
584 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in atombios_adjust_pll()
586 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in atombios_adjust_pll()
589 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; in atombios_adjust_pll()
592 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
595 && !radeon_crtc->ss_enabled) in atombios_adjust_pll()
596 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
598 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
600 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; in atombios_adjust_pll()
603 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in atombios_adjust_pll()
605 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in atombios_adjust_pll()
621 if (radeon_crtc->ss_enabled) { in atombios_adjust_pll()
622 if (radeon_crtc->ss.refdiv) { in atombios_adjust_pll()
623 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
624 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; in atombios_adjust_pll()
628 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
638 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; in atombios_adjust_pll()
640 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; in atombios_adjust_pll()
643 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; in atombios_adjust_pll()
645 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
690 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) in atombios_adjust_pll()
703 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) in atombios_adjust_pll()
731 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
732 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
733 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; in atombios_adjust_pll()
736 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
737 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; in atombios_adjust_pll()
738 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; in atombios_adjust_pll()
957 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_prepare_pll() local
961 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
962 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
964 radeon_crtc->bpc = 8; in atombios_crtc_prepare_pll()
965 radeon_crtc->ss_enabled = false; in atombios_crtc_prepare_pll()
968 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { in atombios_crtc_prepare_pll()
971 radeon_get_connector_for_encoder(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
980 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); in atombios_crtc_prepare_pll()
988 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
989 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, in atombios_crtc_prepare_pll()
994 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
996 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
998 if (!radeon_crtc->ss_enabled) in atombios_crtc_prepare_pll()
999 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1001 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1004 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1006 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1010 radeon_crtc->ss_enabled = false; in atombios_crtc_prepare_pll()
1015 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1017 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1021 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1023 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1028 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1030 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1036 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1038 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1048 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); in atombios_crtc_prepare_pll()
1055 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_set_pll() local
1059 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_set_pll()
1064 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); in atombios_crtc_set_pll()
1069 (radeon_crtc->bpc > 8)) in atombios_crtc_set_pll()
1070 clock = radeon_crtc->adjusted_clock; in atombios_crtc_set_pll()
1072 switch (radeon_crtc->pll_id) { in atombios_crtc_set_pll()
1087 pll->flags = radeon_crtc->pll_flags; in atombios_crtc_set_pll()
1088 pll->reference_div = radeon_crtc->pll_reference_div; in atombios_crtc_set_pll()
1089 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()
1093 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1096 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1099 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1102 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1103 radeon_crtc->crtc_id, &radeon_crtc->ss); in atombios_crtc_set_pll()
1105 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1108 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); in atombios_crtc_set_pll()
1110 if (radeon_crtc->ss_enabled) { in atombios_crtc_set_pll()
1115 (u32)radeon_crtc->ss.percentage) / in atombios_crtc_set_pll()
1116 (100 * (u32)radeon_crtc->ss.percentage_divider); in atombios_crtc_set_pll()
1117 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; in atombios_crtc_set_pll()
1118 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & in atombios_crtc_set_pll()
1120 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) in atombios_crtc_set_pll()
1121 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / in atombios_crtc_set_pll()
1124 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / in atombios_crtc_set_pll()
1126 radeon_crtc->ss.step = step_size; in atombios_crtc_set_pll()
1129 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1130 radeon_crtc->crtc_id, &radeon_crtc->ss); in atombios_crtc_set_pll()
1138 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in dce4_crtc_do_set_base() local
1357 switch (radeon_crtc->crtc_id) { in dce4_crtc_do_set_base()
1383 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1385 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1387 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1389 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1391 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1393 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in dce4_crtc_do_set_base()
1394 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in dce4_crtc_do_set_base()
1401 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1408 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1409 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1410 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1411 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1412 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in dce4_crtc_do_set_base()
1413 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in dce4_crtc_do_set_base()
1416 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in dce4_crtc_do_set_base()
1417 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in dce4_crtc_do_set_base()
1420 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1423 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1427 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1434 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1438 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1459 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in avivo_crtc_do_set_base() local
1589 if (radeon_crtc->crtc_id == 0) in avivo_crtc_do_set_base()
1597 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1600 if (radeon_crtc->crtc_id) { in avivo_crtc_do_set_base()
1608 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1611 radeon_crtc->crtc_offset, (u32) fb_location); in avivo_crtc_do_set_base()
1612 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in avivo_crtc_do_set_base()
1614 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in avivo_crtc_do_set_base()
1617 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1623 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1624 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1625 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1626 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1627 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in avivo_crtc_do_set_base()
1628 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in avivo_crtc_do_set_base()
1631 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in avivo_crtc_do_set_base()
1632 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in avivo_crtc_do_set_base()
1634 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1638 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1642 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1646 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); in avivo_crtc_do_set_base()
1697 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_legacy_atom_fixup() local
1700 switch (radeon_crtc->crtc_id) { in radeon_legacy_atom_fixup()
1727 struct radeon_crtc *test_radeon_crtc; in radeon_get_pll_use_mask()
1755 struct radeon_crtc *test_radeon_crtc; in radeon_get_shared_dp_ppll()
1785 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_get_shared_nondp_ppll() local
1789 struct radeon_crtc *test_radeon_crtc; in radeon_get_shared_nondp_ppll()
1792 adjusted_clock = radeon_crtc->adjusted_clock; in radeon_get_shared_nondp_ppll()
1808 if (test_radeon_crtc->connector == radeon_crtc->connector) { in radeon_get_shared_nondp_ppll()
1817 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && in radeon_get_shared_nondp_ppll()
1864 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_atom_pick_pll() local
1868 to_radeon_encoder(radeon_crtc->encoder); in radeon_atom_pick_pll()
1873 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1920 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1947 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1970 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
2016 return radeon_crtc->crtc_id; in radeon_atom_pick_pll()
2045 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_mode_set() local
2049 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_mode_set()
2056 if (!radeon_crtc->adjusted_clock) in atombios_crtc_mode_set()
2070 if (radeon_crtc->crtc_id == 0) in atombios_crtc_mode_set()
2079 radeon_crtc->hw_mode = *adjusted_mode; in atombios_crtc_mode_set()
2088 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_mode_fixup() local
2095 radeon_crtc->encoder = encoder; in atombios_crtc_mode_fixup()
2096 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); in atombios_crtc_mode_fixup()
2100 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { in atombios_crtc_mode_fixup()
2101 radeon_crtc->encoder = NULL; in atombios_crtc_mode_fixup()
2102 radeon_crtc->connector = NULL; in atombios_crtc_mode_fixup()
2105 if (radeon_crtc->encoder) { in atombios_crtc_mode_fixup()
2107 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_mode_fixup()
2109 radeon_crtc->output_csc = radeon_encoder->output_csc; in atombios_crtc_mode_fixup()
2116 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); in atombios_crtc_mode_fixup()
2118 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && in atombios_crtc_mode_fixup()
2119 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) in atombios_crtc_mode_fixup()
2146 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_crtc_disable() local
2168 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); in atombios_crtc_disable()
2170 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); in atombios_crtc_disable()
2178 i != radeon_crtc->crtc_id && in atombios_crtc_disable()
2179 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { in atombios_crtc_disable()
2187 switch (radeon_crtc->pll_id) { in atombios_crtc_disable()
2191 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_disable()
2200 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_disable()
2207 radeon_crtc->pll_id = ATOM_PPLL_INVALID; in atombios_crtc_disable()
2208 radeon_crtc->adjusted_clock = 0; in atombios_crtc_disable()
2209 radeon_crtc->encoder = NULL; in atombios_crtc_disable()
2210 radeon_crtc->connector = NULL; in atombios_crtc_disable()
2226 struct radeon_crtc *radeon_crtc) in radeon_atombios_init_crtc() argument
2231 switch (radeon_crtc->crtc_id) { in radeon_atombios_init_crtc()
2234 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2237 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2240 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2243 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2246 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2249 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2253 if (radeon_crtc->crtc_id == 1) in radeon_atombios_init_crtc()
2254 radeon_crtc->crtc_offset = in radeon_atombios_init_crtc()
2257 radeon_crtc->crtc_offset = 0; in radeon_atombios_init_crtc()
2259 radeon_crtc->pll_id = ATOM_PPLL_INVALID; in radeon_atombios_init_crtc()
2260 radeon_crtc->adjusted_clock = 0; in radeon_atombios_init_crtc()
2261 radeon_crtc->encoder = NULL; in radeon_atombios_init_crtc()
2262 radeon_crtc->connector = NULL; in radeon_atombios_init_crtc()
2263 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); in radeon_atombios_init_crtc()