Lines Matching refs:rbo
1143 struct radeon_bo *rbo; in dce4_crtc_do_set_base() local
1167 rbo = gem_to_radeon_bo(obj); in dce4_crtc_do_set_base()
1168 r = radeon_bo_reserve(rbo, false); in dce4_crtc_do_set_base()
1173 fb_location = radeon_bo_gpu_offset(rbo); in dce4_crtc_do_set_base()
1175 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); in dce4_crtc_do_set_base()
1177 radeon_bo_unreserve(rbo); in dce4_crtc_do_set_base()
1182 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base()
1183 radeon_bo_unreserve(rbo); in dce4_crtc_do_set_base()
1441 rbo = gem_to_radeon_bo(fb->obj[0]); in dce4_crtc_do_set_base()
1442 r = radeon_bo_reserve(rbo, false); in dce4_crtc_do_set_base()
1445 radeon_bo_unpin(rbo); in dce4_crtc_do_set_base()
1446 radeon_bo_unreserve(rbo); in dce4_crtc_do_set_base()
1463 struct radeon_bo *rbo; in avivo_crtc_do_set_base() local
1484 rbo = gem_to_radeon_bo(obj); in avivo_crtc_do_set_base()
1485 r = radeon_bo_reserve(rbo, false); in avivo_crtc_do_set_base()
1493 fb_location = radeon_bo_gpu_offset(rbo); in avivo_crtc_do_set_base()
1495 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); in avivo_crtc_do_set_base()
1497 radeon_bo_unreserve(rbo); in avivo_crtc_do_set_base()
1501 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base()
1502 radeon_bo_unreserve(rbo); in avivo_crtc_do_set_base()
1649 rbo = gem_to_radeon_bo(fb->obj[0]); in avivo_crtc_do_set_base()
1650 r = radeon_bo_reserve(rbo, false); in avivo_crtc_do_set_base()
1653 radeon_bo_unpin(rbo); in avivo_crtc_do_set_base()
1654 radeon_bo_unreserve(rbo); in avivo_crtc_do_set_base()
2155 struct radeon_bo *rbo; in atombios_crtc_disable() local
2157 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]); in atombios_crtc_disable()
2158 r = radeon_bo_reserve(rbo, false); in atombios_crtc_disable()
2162 radeon_bo_unpin(rbo); in atombios_crtc_disable()
2163 radeon_bo_unreserve(rbo); in atombios_crtc_disable()