Lines Matching refs:dp_info
553 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) in radeon_dp_update_vs_emph() argument
556 atombios_dig_transmitter_setup(dp_info->encoder, in radeon_dp_update_vs_emph()
558 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
561 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, in radeon_dp_update_vs_emph()
562 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
565 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) in radeon_dp_set_tp() argument
570 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { in radeon_dp_set_tp()
582 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); in radeon_dp_set_tp()
592 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, in radeon_dp_set_tp()
593 dp_info->dp_clock, dp_info->enc_id, rtp); in radeon_dp_set_tp()
597 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); in radeon_dp_set_tp()
600 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) in radeon_dp_link_train_init() argument
602 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); in radeon_dp_link_train_init()
607 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); in radeon_dp_link_train_init()
610 if (dp_info->dpcd[3] & 0x1) in radeon_dp_link_train_init()
611 drm_dp_dpcd_writeb(dp_info->aux, in radeon_dp_link_train_init()
614 drm_dp_dpcd_writeb(dp_info->aux, in radeon_dp_link_train_init()
618 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); in radeon_dp_link_train_init()
621 tmp = dp_info->dp_lane_count; in radeon_dp_link_train_init()
622 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) in radeon_dp_link_train_init()
624 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); in radeon_dp_link_train_init()
627 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); in radeon_dp_link_train_init()
628 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); in radeon_dp_link_train_init()
631 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) in radeon_dp_link_train_init()
632 atombios_dig_encoder_setup(dp_info->encoder, in radeon_dp_link_train_init()
635 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, in radeon_dp_link_train_init()
636 dp_info->dp_clock, dp_info->enc_id, 0); in radeon_dp_link_train_init()
639 drm_dp_dpcd_writeb(dp_info->aux, in radeon_dp_link_train_init()
646 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) in radeon_dp_link_train_finish() argument
651 drm_dp_dpcd_writeb(dp_info->aux, in radeon_dp_link_train_finish()
656 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) in radeon_dp_link_train_finish()
657 atombios_dig_encoder_setup(dp_info->encoder, in radeon_dp_link_train_finish()
660 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, in radeon_dp_link_train_finish()
661 dp_info->dp_clock, dp_info->enc_id, 0); in radeon_dp_link_train_finish()
666 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) in radeon_dp_link_train_cr() argument
672 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); in radeon_dp_link_train_cr()
673 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
674 radeon_dp_update_vs_emph(dp_info); in radeon_dp_link_train_cr()
680 dp_info->tries = 0; in radeon_dp_link_train_cr()
683 drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd); in radeon_dp_link_train_cr()
685 if (drm_dp_dpcd_read_link_status(dp_info->aux, in radeon_dp_link_train_cr()
686 dp_info->link_status) <= 0) { in radeon_dp_link_train_cr()
691 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { in radeon_dp_link_train_cr()
696 for (i = 0; i < dp_info->dp_lane_count; i++) { in radeon_dp_link_train_cr()
697 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
700 if (i == dp_info->dp_lane_count) { in radeon_dp_link_train_cr()
705 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
706 ++dp_info->tries; in radeon_dp_link_train_cr()
707 if (dp_info->tries == 5) { in radeon_dp_link_train_cr()
712 dp_info->tries = 0; in radeon_dp_link_train_cr()
714 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
717 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr()
719 radeon_dp_update_vs_emph(dp_info); in radeon_dp_link_train_cr()
726 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in radeon_dp_link_train_cr()
727 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in radeon_dp_link_train_cr()
733 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) in radeon_dp_link_train_ce() argument
737 if (dp_info->tp3_supported) in radeon_dp_link_train_ce()
738 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); in radeon_dp_link_train_ce()
740 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); in radeon_dp_link_train_ce()
743 dp_info->tries = 0; in radeon_dp_link_train_ce()
746 drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); in radeon_dp_link_train_ce()
748 if (drm_dp_dpcd_read_link_status(dp_info->aux, in radeon_dp_link_train_ce()
749 dp_info->link_status) <= 0) { in radeon_dp_link_train_ce()
754 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { in radeon_dp_link_train_ce()
760 if (dp_info->tries > 5) { in radeon_dp_link_train_ce()
766 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_ce()
768 radeon_dp_update_vs_emph(dp_info); in radeon_dp_link_train_ce()
769 dp_info->tries++; in radeon_dp_link_train_ce()
777 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in radeon_dp_link_train_ce()
778 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) in radeon_dp_link_train_ce()
793 struct radeon_dp_link_train_info dp_info; in radeon_dp_link_train() local
814 dp_info.use_dpencoder = true; in radeon_dp_link_train()
818 dp_info.use_dpencoder = false; in radeon_dp_link_train()
821 dp_info.enc_id = 0; in radeon_dp_link_train()
823 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; in radeon_dp_link_train()
825 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; in radeon_dp_link_train()
827 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; in radeon_dp_link_train()
829 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; in radeon_dp_link_train()
834 dp_info.tp3_supported = true; in radeon_dp_link_train()
836 dp_info.tp3_supported = false; in radeon_dp_link_train()
838 dp_info.tp3_supported = false; in radeon_dp_link_train()
841 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in radeon_dp_link_train()
842 dp_info.rdev = rdev; in radeon_dp_link_train()
843 dp_info.encoder = encoder; in radeon_dp_link_train()
844 dp_info.connector = connector; in radeon_dp_link_train()
845 dp_info.dp_lane_count = dig_connector->dp_lane_count; in radeon_dp_link_train()
846 dp_info.dp_clock = dig_connector->dp_clock; in radeon_dp_link_train()
847 dp_info.aux = &radeon_connector->ddc_bus->aux; in radeon_dp_link_train()
849 if (radeon_dp_link_train_init(&dp_info)) in radeon_dp_link_train()
851 if (radeon_dp_link_train_cr(&dp_info)) in radeon_dp_link_train()
853 if (radeon_dp_link_train_ce(&dp_info)) in radeon_dp_link_train()
856 if (radeon_dp_link_train_finish(&dp_info)) in radeon_dp_link_train()