Lines Matching refs:cac_tdp_table
314 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; in ci_populate_tdc_limit()
394 struct radeon_cac_tdp_table *cac_tdp_table = in ci_populate_bapm_vddc_base_leakage_sidd() local
395 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_vddc_base_leakage_sidd()
397 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256; in ci_populate_bapm_vddc_base_leakage_sidd()
398 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256; in ci_populate_bapm_vddc_base_leakage_sidd()
411 struct radeon_cac_tdp_table *cac_tdp_table = in ci_populate_bapm_parameters_in_dpm_table() local
412 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_parameters_in_dpm_table()
418 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
419 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
646 struct radeon_cac_tdp_table *cac_tdp_table = in ci_enable_power_containment() local
647 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_enable_power_containment()
649 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256); in ci_enable_power_containment()
720 struct radeon_cac_tdp_table *cac_tdp_table = in ci_power_control_set_level() local
721 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_power_control_set_level()
731 (s32)cac_tdp_table->configurable_tdp) / 100; in ci_power_control_set_level()
1598 struct radeon_cac_tdp_table *cac_tdp_table =
1599 rdev->pm.dpm.dyn_state.cac_tdp_table;
1603 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1605 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);