Lines Matching refs:smc_state_table
410 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
1280 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
2557 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2565 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2604 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
3245 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3254 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3258 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3260 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3263 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
3265 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3292 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3302 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3307 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3311 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3312 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3313 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3314 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3317 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3319 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3323 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3521 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table()
3543 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3592 (u32 *)&pi->smc_state_table.GraphicsBootLevel); in ci_init_smc_table()
3596 (u32 *)&pi->smc_state_table.MemoryBootLevel); in ci_init_smc_table()
4046 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4048 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4053 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); in ci_update_uvd_dpm()
4088 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); in ci_update_vce_dpm()
4091 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); in ci_update_vce_dpm()
4117 pi->smc_state_table.AcpBootLevel = 0;
4121 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
5787 dpm_table = &pi->smc_state_table; in ci_dpm_init()