Lines Matching refs:SDMA1_REGISTER_OFFSET
166 case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET): in cik_get_allowed_info_register()
3328 WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
4814 RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
4871 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); in cik_gpu_check_soft_reset()
4960 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_soft_reset()
4962 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5161 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
5163 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5514 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5515 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
6160 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
6167 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
6170 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
6185 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6188 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6195 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6198 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6865 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
6866 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
7049 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7220 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); in cik_irq_set()