Lines Matching refs:rlc
5806 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc) in cik_update_rlc() argument
5811 if (tmp != rlc) in cik_update_rlc()
5812 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
6420 if (rdev->rlc.cp_table_ptr == NULL) in cik_init_cp_pg_table()
6424 dst_ptr = rdev->rlc.cp_table_ptr; in cik_init_cp_pg_table()
6616 if (rdev->rlc.cs_data) { in cik_init_gfx_cgpg()
6618 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6619 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6620 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size); in cik_init_gfx_cgpg()
6626 if (rdev->rlc.reg_list) { in cik_init_gfx_cgpg()
6628 for (i = 0; i < rdev->rlc.reg_list_size; i++) in cik_init_gfx_cgpg()
6629 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]); in cik_init_gfx_cgpg()
6637 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in cik_init_gfx_cgpg()
6638 WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8); in cik_init_gfx_cgpg()
6673 if (rdev->rlc.cs_data == NULL) in cik_get_csb_size()
6681 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in cik_get_csb_size()
6705 if (rdev->rlc.cs_data == NULL) in cik_get_csb_buffer()
6717 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in cik_get_csb_buffer()
8310 rdev->rlc.reg_list = spectre_rlc_save_restore_register_list; in cik_startup()
8311 rdev->rlc.reg_list_size = in cik_startup()
8314 rdev->rlc.reg_list = kalindi_rlc_save_restore_register_list; in cik_startup()
8315 rdev->rlc.reg_list_size = in cik_startup()
8319 rdev->rlc.cs_data = ci_cs_data; in cik_startup()
8320 rdev->rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ in cik_startup()
8321 rdev->rlc.cp_table_size += 64 * 1024; /* GDS */ in cik_startup()