Lines Matching refs:radeon_crtc
1296 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in dce4_program_fmt() local
1344 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
1418 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip() local
1419 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in evergreen_page_flip()
1422 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in evergreen_page_flip()
1425 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, in evergreen_page_flip()
1428 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in evergreen_page_flip()
1430 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in evergreen_page_flip()
1433 RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset); in evergreen_page_flip()
1446 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip_pending() local
1449 return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & in evergreen_page_flip_pending()
1677 struct radeon_crtc *radeon_crtc; in evergreen_pm_prepare() local
1682 radeon_crtc = to_radeon_crtc(crtc); in evergreen_pm_prepare()
1683 if (radeon_crtc->enabled) { in evergreen_pm_prepare()
1684 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_prepare()
1686 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_prepare()
1702 struct radeon_crtc *radeon_crtc; in evergreen_pm_finish() local
1707 radeon_crtc = to_radeon_crtc(crtc); in evergreen_pm_finish()
1708 if (radeon_crtc->enabled) { in evergreen_pm_finish()
1709 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_finish()
1711 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_finish()
1826 struct radeon_crtc *radeon_crtc, in evergreen_line_buffer_adjust() argument
1831 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in evergreen_line_buffer_adjust()
1853 if (radeon_crtc->base.enabled && mode) { in evergreen_line_buffer_adjust()
1867 if (radeon_crtc->crtc_id % 2) in evergreen_line_buffer_adjust()
1869 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); in evergreen_line_buffer_adjust()
1882 if (radeon_crtc->base.enabled && mode) { in evergreen_line_buffer_adjust()
2155 struct radeon_crtc *radeon_crtc, in evergreen_program_watermarks() argument
2158 struct drm_display_mode *mode = &radeon_crtc->base.mode; in evergreen_program_watermarks()
2167 u32 pipe_offset = radeon_crtc->crtc_id * 16; in evergreen_program_watermarks()
2171 if (radeon_crtc->base.enabled && num_heads && mode) { in evergreen_program_watermarks()
2199 wm_high.vsc = radeon_crtc->vsc; in evergreen_program_watermarks()
2201 if (radeon_crtc->rmx_type != RMX_OFF) in evergreen_program_watermarks()
2226 wm_low.vsc = radeon_crtc->vsc; in evergreen_program_watermarks()
2228 if (radeon_crtc->rmx_type != RMX_OFF) in evergreen_program_watermarks()
2262 c.full = dfixed_mul(c, radeon_crtc->hsc); in evergreen_program_watermarks()
2274 c.full = dfixed_mul(c, radeon_crtc->hsc); in evergreen_program_watermarks()
2282 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in evergreen_program_watermarks()
2306 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); in evergreen_program_watermarks()
2307 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); in evergreen_program_watermarks()
2310 radeon_crtc->line_time = line_time; in evergreen_program_watermarks()
2311 radeon_crtc->wm_high = latency_watermark_a; in evergreen_program_watermarks()
2312 radeon_crtc->wm_low = latency_watermark_b; in evergreen_program_watermarks()