Lines Matching refs:dst_offset
2803 u64 src_offset, dst_offset, dst2_offset; in evergreen_dma_cs_parse() local
2828 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2829 dst_offset <<= 8; in evergreen_dma_cs_parse()
2836 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2837 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_dma_cs_parse()
2847 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2849 dst_offset, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2870 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2871 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2877 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2879 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2897 dst_offset = radeon_get_ib_value(p, idx + 7); in evergreen_dma_cs_parse()
2898 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2908 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2909 dst_offset <<= 8; in evergreen_dma_cs_parse()
2917 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2919 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2929 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2930 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2936 if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2938 dst_offset + count, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2969 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2970 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2980 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2982 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3009 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3010 dst_offset <<= 8; in evergreen_dma_cs_parse()
3020 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3022 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3071 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3072 dst_offset <<= 8; in evergreen_dma_cs_parse()
3082 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3084 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3108 dst_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3109 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3119 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3120 dst_offset <<= 8; in evergreen_dma_cs_parse()
3128 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3130 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3158 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3159 dst_offset <<= 8; in evergreen_dma_cs_parse()
3169 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3171 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3196 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3197 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; in evergreen_dma_cs_parse()
3198 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3200 dst_offset, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()