Lines Matching refs:ib
450 uint32_t *ib = p->ib.ptr; in evergreen_cs_track_validate_cb() local
472 ib[track->cb_color_slice_idx[id]] = slice; in evergreen_cs_track_validate_cb()
1097 u32 tmp, *ib; in evergreen_cs_handle_reg() local
1100 ib = p->ib.ptr; in evergreen_cs_handle_reg()
1148 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1177 ib[idx] &= ~Z_ARRAY_MODE(0xf); in evergreen_cs_handle_reg()
1179 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1187 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1188 ib[idx] |= DB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1220 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1232 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1244 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1256 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1280 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1300 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1365 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1383 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1451 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1452 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1459 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1479 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1480 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1487 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1504 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1521 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1562 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1578 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1590 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1598 ib[idx] |= 3; in evergreen_cs_handle_reg()
1707 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1721 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1735 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1776 uint32_t *ib; in evergreen_packet3_check() local
1784 ib = p->ib.ptr; in evergreen_packet3_check()
1822 ib[idx + 0] = offset; in evergreen_packet3_check()
1823 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
1868 ib[idx+0] = offset; in evergreen_packet3_check()
1869 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1903 ib[idx+0] = offset; in evergreen_packet3_check()
1904 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1931 ib[idx+1] = offset; in evergreen_packet3_check()
1932 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2024 ib[idx+1] = reloc->gpu_offset; in evergreen_packet3_check()
2025 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2078 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2104 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); in evergreen_packet3_check()
2105 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2165 ib[idx] = offset; in evergreen_packet3_check()
2166 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2203 ib[idx+2] = offset; in evergreen_packet3_check()
2204 ib[idx+3] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2231 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2251 ib[idx+1] = offset & 0xfffffff8; in evergreen_packet3_check()
2252 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2273 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2274 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2295 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2296 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2360 ib[idx+1+(i*8)+1] |= in evergreen_packet3_check()
2368 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); in evergreen_packet3_check()
2369 ib[idx+1+(i*8)+7] |= in evergreen_packet3_check()
2380 tex_dim = ib[idx+1+(i*8)+0] & 0x7; in evergreen_packet3_check()
2381 mip_address = ib[idx+1+(i*8)+3]; in evergreen_packet3_check()
2403 ib[idx+1+(i*8)+2] += toffset; in evergreen_packet3_check()
2404 ib[idx+1+(i*8)+3] += moffset; in evergreen_packet3_check()
2420 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2424 ib[idx+1+(i*8)+0] = offset64; in evergreen_packet3_check()
2425 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in evergreen_packet3_check()
2505 ib[idx+1] = offset; in evergreen_packet3_check()
2506 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2524 ib[idx+3] = offset; in evergreen_packet3_check()
2525 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2553 ib[idx+0] = offset; in evergreen_packet3_check()
2554 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2578 ib[idx+1] = offset; in evergreen_packet3_check()
2579 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2605 ib[idx+3] = offset; in evergreen_packet3_check()
2606 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2654 ib[idx+1] = (offset & 0xfffffffc) | swap; in evergreen_packet3_check()
2655 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2777 for (r = 0; r < p->ib.length_dw; r++) { in evergreen_cs_parse()
2778 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]); in evergreen_cs_parse()
2801 uint32_t *ib = p->ib.ptr; in evergreen_dma_cs_parse() local
2831 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2839 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2840 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2882 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2883 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2884 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2885 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2895 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2899 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2900 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2905 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2906 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2910 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2941 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2942 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2943 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2944 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2954 ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2955 ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2956 ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2957 ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2990 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2991 ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2992 ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2993 ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2994 ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2995 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3030 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3031 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3032 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3033 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3046 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3048 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3049 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3052 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3053 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3055 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3092 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3093 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3094 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3095 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3106 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3110 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3111 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3116 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3117 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3121 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3142 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3143 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3179 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3180 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3181 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3182 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3203 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3204 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in evergreen_dma_cs_parse()
3216 for (r = 0; r < p->ib->length_dw; r++) { in evergreen_dma_cs_parse()
3217 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]); in evergreen_dma_cs_parse()
3348 u32 *ib, struct radeon_cs_packet *pkt) in evergreen_vm_packet3_check() argument
3351 u32 idx_value = ib[idx]; in evergreen_vm_packet3_check()
3408 reg = ib[idx + 5] * 4; in evergreen_vm_packet3_check()
3415 reg = ib[idx + 3] * 4; in evergreen_vm_packet3_check()
3436 command = ib[idx + 4]; in evergreen_vm_packet3_check()
3437 info = ib[idx + 1]; in evergreen_vm_packet3_check()
3474 start_reg = ib[idx + 2]; in evergreen_vm_packet3_check()
3520 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) in evergreen_ib_parse() argument
3528 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); in evergreen_ib_parse()
3529 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); in evergreen_ib_parse()
3540 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); in evergreen_ib_parse()
3541 ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt); in evergreen_ib_parse()
3551 } while (idx < ib->length_dw); in evergreen_ib_parse()
3565 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) in evergreen_dma_ib_parse() argument
3571 header = ib->ptr[idx]; in evergreen_dma_ib_parse()
3588 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3639 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3653 } while (idx < ib->length_dw); in evergreen_dma_ib_parse()