Lines Matching refs:src_offset
2803 u64 src_offset, dst_offset, dst2_offset; in evergreen_dma_cs_parse() local
2868 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2869 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2872 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2874 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2893 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2894 src_offset <<= 8; in evergreen_dma_cs_parse()
2903 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
2904 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2912 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2914 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2927 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2928 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2931 if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2933 src_offset + count, radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2973 src_offset = radeon_get_ib_value(p, idx+3); in evergreen_dma_cs_parse()
2974 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in evergreen_dma_cs_parse()
2975 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2977 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3013 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3014 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3015 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3017 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3075 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3076 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3077 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3079 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3104 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3105 src_offset <<= 8; in evergreen_dma_cs_parse()
3114 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3115 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3123 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3125 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3162 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3163 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3164 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3166 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()