Lines Matching refs:RREG32
80 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) in r100_is_in_vblank()
85 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) in r100_is_in_vblank()
97 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
98 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
100 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
101 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; in r100_is_counter_moving()
125 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) in r100_wait_for_vblank()
128 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) in r100_wait_for_vblank()
184 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
210 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
370 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
379 tmp = RREG32(voltage->gpio.reg); in r100_pm_misc()
471 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); in r100_pm_prepare()
475 tmp = RREG32(RADEON_CRTC_GEN_CNTL); in r100_pm_prepare()
502 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); in r100_pm_finish()
506 tmp = RREG32(RADEON_CRTC_GEN_CNTL); in r100_pm_finish()
524 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) in r100_gui_idle()
546 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) in r100_hpd_sense()
550 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) in r100_hpd_sense()
575 tmp = RREG32(RADEON_FP_GEN_CNTL); in r100_hpd_set_polarity()
583 tmp = RREG32(RADEON_FP2_GEN_CNTL); in r100_hpd_set_polarity()
675 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; in r100_pci_gart_enable()
682 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; in r100_pci_gart_enable()
697 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; in r100_pci_gart_disable()
751 RREG32(RADEON_GEN_INT_CNTL); in r100_irq_set()
763 tmp = RREG32(R_000044_GEN_INT_STATUS); in r100_irq_disable()
769 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); in r100_irq_ack()
832 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; in r100_irq_process()
847 return RREG32(RADEON_CRTC_CRNT_FRAME); in r100_get_vblank_counter()
849 return RREG32(RADEON_CRTC2_CRNT_FRAME); in r100_get_vblank_counter()
983 tmp = RREG32(R_000E40_RBBM_STATUS); in r100_cp_wait_for_idle()
1080 rptr = RREG32(RADEON_CP_RB_RPTR); in r100_gfx_get_rptr()
1088 return RREG32(RADEON_CP_RB_WPTR); in r100_gfx_get_wptr()
1095 (void)RREG32(RADEON_CP_RB_WPTR); in r100_gfx_set_wptr()
2483 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; in r100_rbbm_fifo_wait_for_entry()
2501 tmp = RREG32(RADEON_RBBM_STATUS); in r100_gui_wait_for_idle()
2517 tmp = RREG32(RADEON_MC_STATUS); in r100_mc_wait_for_idle()
2530 rbbm_status = RREG32(R_000E40_RBBM_STATUS); in r100_gpu_is_lockup()
2543 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; in r100_enable_bm()
2552 tmp = RREG32(R_000030_BUS_CNTL); in r100_bm_disable()
2558 tmp = RREG32(RADEON_BUS_CNTL); in r100_bm_disable()
2570 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2575 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2579 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_asic_reset()
2592 RREG32(R_0000F0_RBBM_SOFT_RESET); in r100_asic_reset()
2596 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2600 RREG32(R_0000F0_RBBM_SOFT_RESET); in r100_asic_reset()
2604 status = RREG32(R_000E40_RBBM_STATUS); in r100_asic_reset()
2665 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); in r100_set_common_regs()
2666 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); in r100_set_common_regs()
2667 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); in r100_set_common_regs()
2713 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) in r100_vram_get_type()
2718 tmp = RREG32(RADEON_MEM_CNTL); in r100_vram_get_type()
2729 tmp = RREG32(RADEON_MEM_CNTL); in r100_vram_get_type()
2746 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); in r100_get_accessible_vram()
2774 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) in r100_get_accessible_vram()
2790 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); in r100_vram_init_sizes()
2794 tom = RREG32(RADEON_NB_TOM); in r100_vram_init_sizes()
2799 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in r100_vram_init_sizes()
2824 temp = RREG32(RADEON_CONFIG_CNTL); in r100_vga_set_state()
2842 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; in r100_mc_init()
2857 (void)RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_errata_after_index()
2858 (void)RREG32(RADEON_CRTC_GEN_CNTL); in r100_pll_errata_after_index()
2879 save = RREG32(RADEON_CLOCK_CNTL_INDEX); in r100_pll_errata_after_data()
2882 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_errata_after_data()
2895 data = RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_rreg()
2936 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); in r100_debugfs_rbbm_info_show()
2937 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); in r100_debugfs_rbbm_info_show()
2938 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); in r100_debugfs_rbbm_info_show()
2941 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; in r100_debugfs_rbbm_info_show()
2943 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); in r100_debugfs_rbbm_info_show()
2957 rdp = RREG32(RADEON_CP_RB_RPTR); in r100_debugfs_cp_ring_info_show()
2958 wdp = RREG32(RADEON_CP_RB_WPTR); in r100_debugfs_cp_ring_info_show()
2960 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); in r100_debugfs_cp_ring_info_show()
2982 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); in r100_debugfs_cp_csq_fifo_show()
2983 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); in r100_debugfs_cp_csq_fifo_show()
2984 csq_stat = RREG32(RADEON_CP_CSQ_STAT); in r100_debugfs_cp_csq_fifo_show()
2985 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); in r100_debugfs_cp_csq_fifo_show()
3005 tmp = RREG32(RADEON_CP_CSQ_DATA); in r100_debugfs_cp_csq_fifo_show()
3011 tmp = RREG32(RADEON_CP_CSQ_DATA); in r100_debugfs_cp_csq_fifo_show()
3017 tmp = RREG32(RADEON_CP_CSQ_DATA); in r100_debugfs_cp_csq_fifo_show()
3028 tmp = RREG32(RADEON_CONFIG_MEMSIZE); in r100_debugfs_mc_info_show()
3030 tmp = RREG32(RADEON_MC_FB_LOCATION); in r100_debugfs_mc_info_show()
3032 tmp = RREG32(RADEON_BUS_CNTL); in r100_debugfs_mc_info_show()
3034 tmp = RREG32(RADEON_MC_AGP_LOCATION); in r100_debugfs_mc_info_show()
3036 tmp = RREG32(RADEON_AGP_BASE); in r100_debugfs_mc_info_show()
3038 tmp = RREG32(RADEON_HOST_PATH_CNTL); in r100_debugfs_mc_info_show()
3040 tmp = RREG32(0x01D0); in r100_debugfs_mc_info_show()
3042 tmp = RREG32(RADEON_AIC_LO_ADDR); in r100_debugfs_mc_info_show()
3044 tmp = RREG32(RADEON_AIC_HI_ADDR); in r100_debugfs_mc_info_show()
3046 tmp = RREG32(0x01E4); in r100_debugfs_mc_info_show()
3244 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); in r100_bandwidth_update()
3290 temp = RREG32(RADEON_MEM_TIMING_CNTL); in r100_bandwidth_update()
3330 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); in r100_bandwidth_update()
3351 temp = RREG32(RADEON_MEM_CNTL); in r100_bandwidth_update()
3355 temp = RREG32(R300_MC_IND_INDEX); in r100_bandwidth_update()
3359 temp = RREG32(R300_MC_IND_DATA); in r100_bandwidth_update()
3362 temp = RREG32(R300_MC_READ_CNTL_AB); in r100_bandwidth_update()
3366 temp = RREG32(R300_MC_READ_CNTL_AB); in r100_bandwidth_update()
3502 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); in r100_bandwidth_update()
3525 temp = RREG32(RS400_DISP1_REG_CNTL); in r100_bandwidth_update()
3531 temp = RREG32(RS400_DMIF_MEM_CNTL1); in r100_bandwidth_update()
3542 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); in r100_bandwidth_update()
3558 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); in r100_bandwidth_update()
3617 temp = RREG32(RS400_DISP2_REQ_CNTL1); in r100_bandwidth_update()
3623 temp = RREG32(RS400_DISP2_REQ_CNTL2); in r100_bandwidth_update()
3637 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); in r100_bandwidth_update()
3671 tmp = RREG32(scratch); in r100_ring_test()
3748 tmp = RREG32(scratch); in r100_ib_test()
3778 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); in r100_mc_stop()
3779 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); in r100_mc_stop()
3780 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); in r100_mc_stop()
3782 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); in r100_mc_stop()
3783 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); in r100_mc_stop()
3796 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); in r100_mc_stop()
3916 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r100_startup()
3945 RREG32(R_000E40_RBBM_STATUS), in r100_resume()
3946 RREG32(R_0007C0_CP_STAT)); in r100_resume()
4003 tmp = RREG32(RADEON_CP_CSQ_CNTL); in r100_restore_sanity()
4007 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_restore_sanity()
4011 tmp = RREG32(RADEON_SCRATCH_UMSK); in r100_restore_sanity()
4049 RREG32(R_000E40_RBBM_STATUS), in r100_init()
4050 RREG32(R_0007C0_CP_STAT)); in r100_init()