Lines Matching refs:reloc
1275 struct radeon_bo_list *reloc; in r100_reloc_pitch_offset() local
1278 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_reloc_pitch_offset()
1288 tmp += (((u32)reloc->gpu_offset) >> 10); in r100_reloc_pitch_offset()
1291 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1293 if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset()
1314 struct radeon_bo_list *reloc; in r100_packet3_load_vbpntr() local
1331 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_packet3_load_vbpntr()
1339 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1342 track->arrays[i + 0].robj = reloc->robj; in r100_packet3_load_vbpntr()
1344 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_packet3_load_vbpntr()
1351 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1352 track->arrays[i + 1].robj = reloc->robj; in r100_packet3_load_vbpntr()
1357 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_packet3_load_vbpntr()
1365 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()
1366 track->arrays[i + 0].robj = reloc->robj; in r100_packet3_load_vbpntr()
1563 struct radeon_bo_list *reloc; in r100_packet0_check() local
1596 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_packet0_check()
1603 track->zb.robj = reloc->robj; in r100_packet0_check()
1606 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1609 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_packet0_check()
1616 track->cb[0].robj = reloc->robj; in r100_packet0_check()
1619 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1625 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_packet0_check()
1633 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1635 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1640 ib[idx] = tmp + ((u32)reloc->gpu_offset); in r100_packet0_check()
1642 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1643 track->textures[i].robj = reloc->robj; in r100_packet0_check()
1652 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_packet0_check()
1660 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1661 track->textures[0].cube_info[i].robj = reloc->robj; in r100_packet0_check()
1670 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_packet0_check()
1678 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1679 track->textures[1].cube_info[i].robj = reloc->robj; in r100_packet0_check()
1688 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_packet0_check()
1696 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1697 track->textures[2].cube_info[i].robj = reloc->robj; in r100_packet0_check()
1706 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_packet0_check()
1714 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1716 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1777 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_packet0_check()
1784 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1921 struct radeon_bo_list *reloc; in r100_packet3_check() local
1937 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_packet3_check()
1943 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); in r100_packet3_check()
1944 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); in r100_packet3_check()
1951 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in r100_packet3_check()
1957 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); in r100_packet3_check()
1961 track->arrays[0].robj = reloc->robj; in r100_packet3_check()