Lines Matching refs:RREG32
127 r = RREG32(R600_RCU_DATA); in r600_rcu_rreg()
149 r = RREG32(R600_UVD_CTX_DATA); in r600_uvd_ctx_rreg()
183 *val = RREG32(reg); in r600_get_allowed_info_register()
352 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> in rv6xx_get_temp()
797 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) in r600_gui_idle()
811 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
815 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
819 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
823 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
828 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
832 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) in r600_hpd_sense()
841 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) in r600_hpd_sense()
845 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) in r600_hpd_sense()
849 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) in r600_hpd_sense()
868 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_hpd_set_polarity()
876 tmp = RREG32(DC_HPD2_INT_CONTROL); in r600_hpd_set_polarity()
884 tmp = RREG32(DC_HPD3_INT_CONTROL); in r600_hpd_set_polarity()
892 tmp = RREG32(DC_HPD4_INT_CONTROL); in r600_hpd_set_polarity()
900 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_hpd_set_polarity()
909 tmp = RREG32(DC_HPD6_INT_CONTROL); in r600_hpd_set_polarity()
922 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); in r600_hpd_set_polarity()
930 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); in r600_hpd_set_polarity()
938 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); in r600_hpd_set_polarity()
1099 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); in r600_pcie_gart_tlb_flush()
1269 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; in r600_mc_wait_for_idle()
1284 r = RREG32(R_0028FC_MC_DATA); in rs780_mc_rreg()
1424 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; in r600_vram_gtt_location()
1442 tmp = RREG32(RAMCFG); in r600_mc_init()
1450 tmp = RREG32(CHMAP); in r600_mc_init()
1471 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1472 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1556 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); in r600_set_bios_scratch_engine_hung()
1569 RREG32(R_008010_GRBM_STATUS)); in r600_print_gpu_status_regs()
1571 RREG32(R_008014_GRBM_STATUS2)); in r600_print_gpu_status_regs()
1573 RREG32(R_000E50_SRBM_STATUS)); in r600_print_gpu_status_regs()
1575 RREG32(CP_STALLED_STAT1)); in r600_print_gpu_status_regs()
1577 RREG32(CP_STALLED_STAT2)); in r600_print_gpu_status_regs()
1579 RREG32(CP_BUSY_STAT)); in r600_print_gpu_status_regs()
1581 RREG32(CP_STAT)); in r600_print_gpu_status_regs()
1583 RREG32(DMA_STATUS_REG)); in r600_print_gpu_status_regs()
1593 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { in r600_is_display_hung()
1594 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
1602 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
1621 tmp = RREG32(R_008010_GRBM_STATUS); in r600_gpu_check_soft_reset()
1646 tmp = RREG32(DMA_STATUS_REG); in r600_gpu_check_soft_reset()
1651 tmp = RREG32(R_000E50_SRBM_STATUS); in r600_gpu_check_soft_reset()
1708 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_soft_reset()
1784 tmp = RREG32(R_008020_GRBM_SOFT_RESET); in r600_gpu_soft_reset()
1788 tmp = RREG32(R_008020_GRBM_SOFT_RESET); in r600_gpu_soft_reset()
1794 tmp = RREG32(R_008020_GRBM_SOFT_RESET); in r600_gpu_soft_reset()
1798 tmp = RREG32(SRBM_SOFT_RESET); in r600_gpu_soft_reset()
1802 tmp = RREG32(SRBM_SOFT_RESET); in r600_gpu_soft_reset()
1808 tmp = RREG32(SRBM_SOFT_RESET); in r600_gpu_soft_reset()
1839 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_pci_config_reset()
1857 tmp = RREG32(BUS_CNTL); in r600_gpu_pci_config_reset()
1861 tmp = RREG32(BIF_SCRATCH0); in r600_gpu_pci_config_reset()
1875 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) in r600_gpu_pci_config_reset()
2087 ramcfg = RREG32(RAMCFG); in r600_gpu_init()
2119 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; in r600_gpu_init()
2124 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; in r600_gpu_init()
2159 tmp = RREG32(SX_DEBUG_1); in r600_gpu_init()
2184 tmp = RREG32(SQ_MS_FIFO_SIZES); in r600_gpu_init()
2203 sq_config = RREG32(SQ_CONFIG); in r600_gpu_init()
2377 tmp = RREG32(HDP_HOST_PATH_CNTL); in r600_gpu_init()
2380 tmp = RREG32(ARB_POP); in r600_gpu_init()
2402 (void)RREG32(PCIE_PORT_INDEX); in r600_pciep_rreg()
2403 r = RREG32(PCIE_PORT_DATA); in r600_pciep_rreg()
2414 (void)RREG32(PCIE_PORT_INDEX); in r600_pciep_wreg()
2416 (void)RREG32(PCIE_PORT_DATA); in r600_pciep_wreg()
2626 rptr = RREG32(R600_CP_RB_RPTR); in r600_gfx_get_rptr()
2634 return RREG32(R600_CP_RB_WPTR); in r600_gfx_get_wptr()
2641 (void)RREG32(R600_CP_RB_WPTR); in r600_gfx_set_wptr()
2662 RREG32(GRBM_SOFT_RESET); in r600_cp_load_microcode()
2725 RREG32(GRBM_SOFT_RESET); in r600_cp_resume()
2847 tmp = RREG32(scratch); in r600_ring_test()
3194 temp = RREG32(CONFIG_CNTL); in r600_vga_set_state()
3436 tmp = RREG32(scratch); in r600_ib_test()
3537 RREG32(SRBM_SOFT_RESET); in r600_rlc_stop()
3540 RREG32(SRBM_SOFT_RESET); in r600_rlc_stop()
3592 u32 ih_cntl = RREG32(IH_CNTL); in r600_enable_interrupts()
3593 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_enable_interrupts()
3604 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_disable_interrupts()
3605 u32 ih_cntl = RREG32(IH_CNTL); in r600_disable_interrupts()
3623 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_disable_interrupt_state()
3632 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3634 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3636 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3638 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3641 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3643 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3645 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3647 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3650 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3652 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3658 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_disable_interrupt_state()
3660 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_disable_interrupt_state()
3662 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_disable_interrupt_state()
3664 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3666 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3698 interrupt_cntl = RREG32(INTERRUPT_CNTL); in r600_irq_init()
3784 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3785 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3786 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3787 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3789 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3790 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3791 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()
3792 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()
3794 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()
3795 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()
3798 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3799 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3800 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3801 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()
3802 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_irq_set()
3805 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_irq_set()
3808 thermal_int = RREG32(CG_THERMAL_INT) & in r600_irq_set()
3811 thermal_int = RREG32(RV770_CG_THERMAL_INT) & in r600_irq_set()
3907 RREG32(R_000E50_SRBM_STATUS); in r600_irq_set()
3917 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3918 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3919 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); in r600_irq_ack()
3921 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); in r600_irq_ack()
3922 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); in r600_irq_ack()
3924 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3925 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); in r600_irq_ack()
3928 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3929 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3931 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3932 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); in r600_irq_ack()
3934 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3935 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3951 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_irq_ack()
3955 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); in r600_irq_ack()
3962 tmp = RREG32(DC_HPD2_INT_CONTROL); in r600_irq_ack()
3966 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); in r600_irq_ack()
3973 tmp = RREG32(DC_HPD3_INT_CONTROL); in r600_irq_ack()
3977 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); in r600_irq_ack()
3983 tmp = RREG32(DC_HPD4_INT_CONTROL); in r600_irq_ack()
3989 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_irq_ack()
3994 tmp = RREG32(DC_HPD6_INT_CONTROL); in r600_irq_ack()
3999 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); in r600_irq_ack()
4004 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); in r600_irq_ack()
4010 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); in r600_irq_ack()
4016 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); in r600_irq_ack()
4020 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); in r600_irq_ack()
4044 wptr = RREG32(IH_RB_WPTR); in r600_get_ih_wptr()
4055 tmp = RREG32(IH_RB_CNTL); in r600_get_ih_wptr()
4107 RREG32(IH_RB_WPTR); in r600_irq_process()
4549 link_cntl2 = RREG32(0x4088); in r600_pcie_gen2_enable()
4563 tmp = RREG32(0x541c); in r600_pcie_gen2_enable()
4613 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | in r600_get_gpu_clock_counter()
4614 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in r600_get_gpu_clock_counter()