Lines Matching refs:WREG32_PLL
402 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
406 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
412 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
418 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
425 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp); in radeon_legacy_set_engine_clock()
434 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
438 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
444 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
465 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
471 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_engine_clock()
496 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
519 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
524 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
529 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
545 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
554 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
572 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
577 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
582 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
598 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
603 WREG32_PLL(RADEON_MCLK_MISC, tmp); in radeon_legacy_set_clock_gating()
635 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
640 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
647 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
658 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); in radeon_legacy_set_clock_gating()
663 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); in radeon_legacy_set_clock_gating()
687 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
703 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
715 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); in radeon_legacy_set_clock_gating()
729 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
736 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
750 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
762 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
766 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
772 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
789 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
795 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
806 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
810 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
817 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
823 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()
840 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
867 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
877 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
885 WREG32_PLL(RADEON_MCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
894 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); in radeon_legacy_set_clock_gating()
907 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_set_clock_gating()
913 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating()