Lines Matching refs:WREG32_P
317 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_s()
324 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_v()
332 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_enable_engine_spread_spectrum()
335 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_enable_engine_spread_spectrum()
342 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK); in rv6xx_set_memory_spread_spectrum_clk_s()
348 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK); in rv6xx_set_memory_spread_spectrum_clk_v()
355 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN); in rv6xx_enable_memory_spread_spectrum()
357 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv6xx_enable_memory_spread_spectrum()
364 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); in rv6xx_enable_dynamic_spread_spectrum()
366 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); in rv6xx_enable_dynamic_spread_spectrum()
373 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_enable_post_divider()
376 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN); in rv6xx_memory_clock_entry_enable_post_divider()
382 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_post_divider()
389 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider), in rv6xx_memory_clock_entry_set_feedback_divider()
396 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_reference_divider()
402 WREG32_P(VID_RT, BRT(rt), ~BRT_MASK); in rv6xx_vid_response_set_brt()
407 WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC); in rv6xx_enable_engine_feedback_and_reference_sync()
734 WREG32_P(VID_UPPER_GPIO_CNTL, MEDIUM_BACKBIAS_VALUE, ~MEDIUM_BACKBIAS_VALUE); in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
736 WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~MEDIUM_BACKBIAS_VALUE); in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
739 WREG32_P(VID_UPPER_GPIO_CNTL, HIGH_BACKBIAS_VALUE, ~HIGH_BACKBIAS_VALUE); in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
741 WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE); in rv6xx_program_backbias_stepping_parameters_except_lowest_entry()
776 WREG32_P(VID_UPPER_GPIO_CNTL, LOW_BACKBIAS_VALUE, ~LOW_BACKBIAS_VALUE); in rv6xx_program_backbias_stepping_parameters_lowest_entry()
778 WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~LOW_BACKBIAS_VALUE); in rv6xx_program_backbias_stepping_parameters_lowest_entry()
991 WREG32_P(MCLK_PWRMGT_CNTL, USE_DISPLAY_GAP, ~USE_DISPLAY_GAP); in rv6xx_enable_display_gap()
993 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP); in rv6xx_enable_display_gap()
1173 WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL, in rv6xx_enable_backbias()
1176 WREG32_P(GENERAL_PWRMGT, 0, in rv6xx_enable_backbias()
1212 WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW), in rv6xx_set_sw_voltage_to_safe()
1224 WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW), in rv6xx_set_sw_voltage_to_low()
1237 WREG32_P(GENERAL_PWRMGT, BACKBIAS_VALUE, ~BACKBIAS_VALUE); in rv6xx_set_safe_backbias()
1239 WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE); in rv6xx_set_safe_backbias()
1258 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); in rv6xx_enable_dynamic_voltage_control()
1260 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); in rv6xx_enable_dynamic_voltage_control()
1267 WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL, ~BACKBIAS_DPM_CNTL); in rv6xx_enable_dynamic_backbias_control()
1269 WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_DPM_CNTL); in rv6xx_enable_dynamic_backbias_control()
1380 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); in rv6xx_set_dpm_event_sources()
1382 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); in rv6xx_set_dpm_event_sources()
1384 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); in rv6xx_set_dpm_event_sources()
1488 WREG32_P(DCE3_LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG); in rv6xx_reset_lvtm_data_sync()
1490 WREG32_P(LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG); in rv6xx_reset_lvtm_data_sync()