Lines Matching refs:radeon_crtc
1967 struct radeon_crtc *radeon_crtc, in dce6_line_buffer_adjust() argument
1972 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce6_line_buffer_adjust()
1986 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust()
1999 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, in dce6_line_buffer_adjust()
2011 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust()
2294 struct radeon_crtc *radeon_crtc, in dce6_program_watermarks() argument
2297 struct drm_display_mode *mode = &radeon_crtc->base.mode; in dce6_program_watermarks()
2309 if (radeon_crtc->base.enabled && num_heads && mode) { in dce6_program_watermarks()
2341 wm_high.vsc = radeon_crtc->vsc; in dce6_program_watermarks()
2343 if (radeon_crtc->rmx_type != RMX_OFF) in dce6_program_watermarks()
2368 wm_low.vsc = radeon_crtc->vsc; in dce6_program_watermarks()
2370 if (radeon_crtc->rmx_type != RMX_OFF) in dce6_program_watermarks()
2406 c.full = dfixed_mul(c, radeon_crtc->hsc); in dce6_program_watermarks()
2418 c.full = dfixed_mul(c, radeon_crtc->hsc); in dce6_program_watermarks()
2426 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce6_program_watermarks()
2430 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks()
2434 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2435 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()
2439 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks()
2442 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2443 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()
2447 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); in dce6_program_watermarks()
2450 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); in dce6_program_watermarks()
2451 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); in dce6_program_watermarks()
2454 radeon_crtc->line_time = line_time; in dce6_program_watermarks()
2455 radeon_crtc->wm_high = latency_watermark_a; in dce6_program_watermarks()
2456 radeon_crtc->wm_low = latency_watermark_b; in dce6_program_watermarks()