Lines Matching refs:radeon_ring_write
3376 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_fence_ring_emit()
3377 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_fence_ring_emit()
3378 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3379 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_fence_ring_emit()
3380 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | in si_fence_ring_emit()
3384 radeon_ring_write(ring, 0xFFFFFFFF); in si_fence_ring_emit()
3385 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3386 radeon_ring_write(ring, 10); /* poll interval */ in si_fence_ring_emit()
3388 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in si_fence_ring_emit()
3389 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); in si_fence_ring_emit()
3390 radeon_ring_write(ring, lower_32_bits(addr)); in si_fence_ring_emit()
3391 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in si_fence_ring_emit()
3392 radeon_ring_write(ring, fence->seq); in si_fence_ring_emit()
3393 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3407 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in si_ring_ib_execute()
3408 radeon_ring_write(ring, 0); in si_ring_ib_execute()
3415 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3416 radeon_ring_write(ring, ((ring->rptr_save_reg - in si_ring_ib_execute()
3418 radeon_ring_write(ring, next_rptr); in si_ring_ib_execute()
3421 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_ring_ib_execute()
3422 radeon_ring_write(ring, (1 << 8)); in si_ring_ib_execute()
3423 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in si_ring_ib_execute()
3424 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in si_ring_ib_execute()
3425 radeon_ring_write(ring, next_rptr); in si_ring_ib_execute()
3431 radeon_ring_write(ring, header); in si_ring_ib_execute()
3432 radeon_ring_write(ring, in si_ring_ib_execute()
3437 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in si_ring_ib_execute()
3438 radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); in si_ring_ib_execute()
3442 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3443 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_ring_ib_execute()
3444 radeon_ring_write(ring, vm_id); in si_ring_ib_execute()
3445 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_ring_ib_execute()
3446 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | in si_ring_ib_execute()
3450 radeon_ring_write(ring, 0xFFFFFFFF); in si_ring_ib_execute()
3451 radeon_ring_write(ring, 0); in si_ring_ib_execute()
3452 radeon_ring_write(ring, 10); /* poll interval */ in si_ring_ib_execute()
3567 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in si_cp_start()
3568 radeon_ring_write(ring, 0x1); in si_cp_start()
3569 radeon_ring_write(ring, 0x0); in si_cp_start()
3570 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1); in si_cp_start()
3571 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); in si_cp_start()
3572 radeon_ring_write(ring, 0); in si_cp_start()
3573 radeon_ring_write(ring, 0); in si_cp_start()
3576 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in si_cp_start()
3577 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in si_cp_start()
3578 radeon_ring_write(ring, 0xc000); in si_cp_start()
3579 radeon_ring_write(ring, 0xe000); in si_cp_start()
3591 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_cp_start()
3592 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in si_cp_start()
3595 radeon_ring_write(ring, si_default_state[i]); in si_cp_start()
3597 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_cp_start()
3598 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in si_cp_start()
3601 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
3602 radeon_ring_write(ring, 0); in si_cp_start()
3604 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in si_cp_start()
3605 radeon_ring_write(ring, 0x00000316); in si_cp_start()
3606 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in si_cp_start()
3607 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ in si_cp_start()
3616 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
3617 radeon_ring_write(ring, 0); in si_cp_start()
5075 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush()
5076 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | in si_vm_flush()
5080 radeon_ring_write(ring, in si_vm_flush()
5083 radeon_ring_write(ring, in si_vm_flush()
5086 radeon_ring_write(ring, 0); in si_vm_flush()
5087 radeon_ring_write(ring, pd_addr >> 12); in si_vm_flush()
5090 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush()
5091 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | in si_vm_flush()
5093 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); in si_vm_flush()
5094 radeon_ring_write(ring, 0); in si_vm_flush()
5095 radeon_ring_write(ring, 0x1); in si_vm_flush()
5098 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush()
5099 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | in si_vm_flush()
5101 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in si_vm_flush()
5102 radeon_ring_write(ring, 0); in si_vm_flush()
5103 radeon_ring_write(ring, 1 << vm_id); in si_vm_flush()
5106 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in si_vm_flush()
5107 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ in si_vm_flush()
5109 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in si_vm_flush()
5110 radeon_ring_write(ring, 0); in si_vm_flush()
5111 radeon_ring_write(ring, 0); /* ref */ in si_vm_flush()
5112 radeon_ring_write(ring, 0); /* mask */ in si_vm_flush()
5113 radeon_ring_write(ring, 0x20); /* poll interval */ in si_vm_flush()
5116 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in si_vm_flush()
5117 radeon_ring_write(ring, 0x0); in si_vm_flush()