Lines Matching refs:smc_state
2268 SISLANDS_SMC_SWSTATE *smc_state) in si_populate_power_containment_values() argument
2291 if (smc_state->levelCount != state->performance_level_count) in si_populate_power_containment_values()
2296 smc_state->levels[0].dpm2.MaxPS = 0; in si_populate_power_containment_values()
2297 smc_state->levels[0].dpm2.NearTDPDec = 0; in si_populate_power_containment_values()
2298 smc_state->levels[0].dpm2.AboveSafeInc = 0; in si_populate_power_containment_values()
2299 smc_state->levels[0].dpm2.BelowSafeInc = 0; in si_populate_power_containment_values()
2300 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; in si_populate_power_containment_values()
2350 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma… in si_populate_power_containment_values()
2351 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; in si_populate_power_containment_values()
2352 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; in si_populate_power_containment_values()
2353 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; in si_populate_power_containment_values()
2354 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); in si_populate_power_containment_values()
2362 SISLANDS_SMC_SWSTATE *smc_state) in si_populate_sq_ramping_values() argument
2373 if (smc_state->levelCount != state->performance_level_count) in si_populate_sq_ramping_values()
2410 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); in si_populate_sq_ramping_values()
2411 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); in si_populate_sq_ramping_values()
4945 SISLANDS_SMC_SWSTATE *smc_state) in si_populate_smc_sp() argument
4952 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); in si_populate_smc_sp()
4954 smc_state->levels[ps->performance_level_count - 1].bSP = in si_populate_smc_sp()
5069 SISLANDS_SMC_SWSTATE *smc_state) in si_populate_smc_t() argument
5083 smc_state->levels[0].aT = cpu_to_be32(a_t); in si_populate_smc_t()
5087 smc_state->levels[0].aT = cpu_to_be32(0); in si_populate_smc_t()
5103 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; in si_populate_smc_t()
5105 smc_state->levels[i].aT = cpu_to_be32(a_t); in si_populate_smc_t()
5110 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); in si_populate_smc_t()
5172 SISLANDS_SMC_SWSTATE *smc_state) in si_convert_power_state_to_smc() argument
5190 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; in si_convert_power_state_to_smc()
5196 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; in si_convert_power_state_to_smc()
5198 smc_state->levelCount = 0; in si_convert_power_state_to_smc()
5203 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; in si_convert_power_state_to_smc()
5205 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; in si_convert_power_state_to_smc()
5210 &smc_state->levels[i]); in si_convert_power_state_to_smc()
5211 smc_state->levels[i].arbRefreshState = in si_convert_power_state_to_smc()
5218 smc_state->levels[i].displayWatermark = in si_convert_power_state_to_smc()
5222 smc_state->levels[i].displayWatermark = (i < 2) ? in si_convert_power_state_to_smc()
5226 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; in si_convert_power_state_to_smc()
5228 smc_state->levels[i].ACIndex = 0; in si_convert_power_state_to_smc()
5230 smc_state->levelCount++; in si_convert_power_state_to_smc()
5237 si_populate_smc_sp(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5239 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5243 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5247 return si_populate_smc_t(rdev, radeon_state, smc_state); in si_convert_power_state_to_smc()
5258 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; in si_upload_sw_state() local
5259 size_t state_size = struct_size(smc_state, levels, in si_upload_sw_state()
5262 memset(smc_state, 0, state_size); in si_upload_sw_state()
5264 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); in si_upload_sw_state()
5268 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, in si_upload_sw_state()
5283 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState; in si_upload_ulv_state() local
5286 memset(smc_state, 0, state_size); in si_upload_ulv_state()
5288 ret = si_populate_ulv_state(rdev, smc_state); in si_upload_ulv_state()
5290 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, in si_upload_ulv_state()