Lines Matching refs:dsi
357 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) in dsi_write() argument
359 writel(val, dsi->base + reg); in dsi_write()
362 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg) in dsi_read() argument
364 return readl(dsi->base + reg); in dsi_read()
367 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, in dw_mipi_dsi_phy_write() argument
376 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
378 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
381 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
383 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
386 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
392 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) in ns2bc() argument
394 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); in ns2bc()
400 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) in ns2ui() argument
402 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); in ns2ui()
407 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_init() local
410 if (dsi->phy) in dw_mipi_dsi_phy_init()
425 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; in dw_mipi_dsi_phy_init()
427 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_phy_init()
429 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_phy_init()
431 dsi->lane_mbps); in dw_mipi_dsi_phy_init()
435 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
437 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); in dw_mipi_dsi_phy_init()
441 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, in dw_mipi_dsi_phy_init()
447 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, in dw_mipi_dsi_phy_init()
449 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, in dw_mipi_dsi_phy_init()
453 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, in dw_mipi_dsi_phy_init()
456 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
457 INPUT_DIVIDER(dsi->input_div)); in dw_mipi_dsi_phy_init()
458 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
459 LOOP_DIV_LOW_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
467 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, in dw_mipi_dsi_phy_init()
469 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
470 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
472 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, in dw_mipi_dsi_phy_init()
475 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, in dw_mipi_dsi_phy_init()
477 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, in dw_mipi_dsi_phy_init()
480 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, in dw_mipi_dsi_phy_init()
484 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, in dw_mipi_dsi_phy_init()
487 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, in dw_mipi_dsi_phy_init()
492 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
493 TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
494 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
495 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); in dw_mipi_dsi_phy_init()
496 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
497 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); in dw_mipi_dsi_phy_init()
498 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
499 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); in dw_mipi_dsi_phy_init()
500 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
501 BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
502 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, in dw_mipi_dsi_phy_init()
503 BIT(5) | (ns2bc(dsi, 60) + 7)); in dw_mipi_dsi_phy_init()
505 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
506 TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
507 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
508 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); in dw_mipi_dsi_phy_init()
509 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
510 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); in dw_mipi_dsi_phy_init()
511 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
512 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); in dw_mipi_dsi_phy_init()
513 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
514 BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
516 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
523 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_power_on() local
526 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi_phy_power_on()
528 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); in dw_mipi_dsi_phy_power_on()
532 phy_configure(dsi->phy, &dsi->phy_opts); in dw_mipi_dsi_phy_power_on()
533 phy_power_on(dsi->phy); in dw_mipi_dsi_phy_power_on()
538 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_power_off() local
540 phy_power_off(dsi->phy); in dw_mipi_dsi_phy_power_off()
548 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_get_lane_mbps() local
560 dsi->format = format; in dw_mipi_dsi_get_lane_mbps()
561 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in dw_mipi_dsi_get_lane_mbps()
563 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
565 dsi->format); in dw_mipi_dsi_get_lane_mbps()
576 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
581 if (dsi->phy) { in dw_mipi_dsi_get_lane_mbps()
584 &dsi->phy_opts.mipi_dphy); in dw_mipi_dsi_get_lane_mbps()
585 dsi->lane_mbps = target_mbps; in dw_mipi_dsi_get_lane_mbps()
586 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
591 fin = clk_get_rate(dsi->pllref_clk); in dw_mipi_dsi_get_lane_mbps()
634 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
635 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
636 dsi->input_div = best_prediv; in dw_mipi_dsi_get_lane_mbps()
637 dsi->feedback_div = best_fbdiv; in dw_mipi_dsi_get_lane_mbps()
639 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); in dw_mipi_dsi_get_lane_mbps()
731 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) in dw_mipi_dsi_rockchip_config() argument
733 if (dsi->cdata->lanecfg1_grf_reg) in dw_mipi_dsi_rockchip_config()
734 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, in dw_mipi_dsi_rockchip_config()
735 dsi->cdata->lanecfg1); in dw_mipi_dsi_rockchip_config()
737 if (dsi->cdata->lanecfg2_grf_reg) in dw_mipi_dsi_rockchip_config()
738 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, in dw_mipi_dsi_rockchip_config()
739 dsi->cdata->lanecfg2); in dw_mipi_dsi_rockchip_config()
741 if (dsi->cdata->enable_grf_reg) in dw_mipi_dsi_rockchip_config()
742 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, in dw_mipi_dsi_rockchip_config()
743 dsi->cdata->enable); in dw_mipi_dsi_rockchip_config()
746 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, in dw_mipi_dsi_rockchip_set_lcdsel() argument
749 if (dsi->cdata->lcdsel_grf_reg) in dw_mipi_dsi_rockchip_set_lcdsel()
750 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, in dw_mipi_dsi_rockchip_set_lcdsel()
751 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); in dw_mipi_dsi_rockchip_set_lcdsel()
760 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_atomic_check() local
762 switch (dsi->format) { in dw_mipi_dsi_encoder_atomic_check()
778 if (dsi->slave) in dw_mipi_dsi_encoder_atomic_check()
786 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_enable() local
789 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, in dw_mipi_dsi_encoder_enable()
790 &dsi->encoder.encoder); in dw_mipi_dsi_encoder_enable()
799 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
801 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_encoder_enable()
805 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); in dw_mipi_dsi_encoder_enable()
806 if (dsi->slave) in dw_mipi_dsi_encoder_enable()
807 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); in dw_mipi_dsi_encoder_enable()
809 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
818 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, in rockchip_dsi_drm_create_encoder() argument
821 struct drm_encoder *encoder = &dsi->encoder.encoder; in rockchip_dsi_drm_create_encoder()
825 dsi->dev->of_node); in rockchip_dsi_drm_create_encoder()
839 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) in dw_mipi_dsi_rockchip_find_second() argument
844 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); in dw_mipi_dsi_rockchip_find_second()
846 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); in dw_mipi_dsi_rockchip_find_second()
855 if (node == dsi->dev->of_node) in dw_mipi_dsi_rockchip_find_second()
902 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_bind() local
908 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_bind()
913 master1 = of_property_read_bool(dsi->dev->of_node, in dw_mipi_dsi_rockchip_bind()
919 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); in dw_mipi_dsi_rockchip_bind()
924 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); in dw_mipi_dsi_rockchip_bind()
930 dsi->is_slave = true; in dw_mipi_dsi_rockchip_bind()
934 dsi->slave = dev_get_drvdata(second); in dw_mipi_dsi_rockchip_bind()
935 if (!dsi->slave) { in dw_mipi_dsi_rockchip_bind()
940 dsi->slave->is_slave = true; in dw_mipi_dsi_rockchip_bind()
941 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); in dw_mipi_dsi_rockchip_bind()
945 pm_runtime_get_sync(dsi->dev); in dw_mipi_dsi_rockchip_bind()
946 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
947 pm_runtime_get_sync(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
949 ret = clk_prepare_enable(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
961 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
963 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_bind()
967 dw_mipi_dsi_rockchip_config(dsi); in dw_mipi_dsi_rockchip_bind()
968 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
969 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_bind()
971 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
973 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); in dw_mipi_dsi_rockchip_bind()
978 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, in dw_mipi_dsi_rockchip_bind()
981 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); in dw_mipi_dsi_rockchip_bind()
987 dsi->dsi_bound = true; in dw_mipi_dsi_rockchip_bind()
992 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
994 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_bind()
995 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
996 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
1005 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_unbind() local
1007 if (dsi->is_slave) in dw_mipi_dsi_rockchip_unbind()
1010 dsi->dsi_bound = false; in dw_mipi_dsi_rockchip_unbind()
1012 dw_mipi_dsi_unbind(dsi->dmd); in dw_mipi_dsi_rockchip_unbind()
1014 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_unbind()
1016 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_unbind()
1017 if (dsi->slave) in dw_mipi_dsi_rockchip_unbind()
1018 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_unbind()
1029 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_rockchip_host_attach() local
1033 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1035 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_rockchip_host_attach()
1036 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_rockchip_host_attach()
1037 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1041 dsi->usage_mode = DW_DSI_USAGE_DSI; in dw_mipi_dsi_rockchip_host_attach()
1042 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1044 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_attach()
1046 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", in dw_mipi_dsi_rockchip_host_attach()
1051 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_host_attach()
1069 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1070 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_attach()
1071 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1078 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_rockchip_host_detach() local
1081 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_host_detach()
1085 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_detach()
1087 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1088 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_detach()
1089 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1126 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_init() local
1129 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1131 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_dphy_init()
1132 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_dphy_init()
1133 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1137 dsi->usage_mode = DW_DSI_USAGE_PHY; in dw_mipi_dsi_dphy_init()
1138 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1140 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1144 if (dsi->cdata->dphy_rx_init) { in dw_mipi_dsi_dphy_init()
1145 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_init()
1149 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1151 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1155 ret = dsi->cdata->dphy_rx_init(phy); in dw_mipi_dsi_dphy_init()
1156 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1157 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1165 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1167 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1168 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_init()
1169 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1176 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_exit() local
1178 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_exit()
1180 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1181 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_exit()
1182 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1190 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_configure() local
1197 dsi->dphy_config = *config; in dw_mipi_dsi_dphy_configure()
1198 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); in dw_mipi_dsi_dphy_configure()
1205 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_power_on() local
1208 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", in dw_mipi_dsi_dphy_power_on()
1209 dsi->dphy_config.lanes, dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1211 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1213 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", in dw_mipi_dsi_dphy_power_on()
1214 dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1218 ret = pm_runtime_resume_and_get(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1220 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1224 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1226 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1230 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1232 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1236 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1238 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1243 if (dsi->cdata->dphy_rx_power_on) { in dw_mipi_dsi_dphy_power_on()
1244 ret = dsi->cdata->dphy_rx_power_on(phy); in dw_mipi_dsi_dphy_power_on()
1246 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1255 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); in dw_mipi_dsi_dphy_power_on()
1256 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, in dw_mipi_dsi_dphy_power_on()
1258 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); in dw_mipi_dsi_dphy_power_on()
1259 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); in dw_mipi_dsi_dphy_power_on()
1260 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); in dw_mipi_dsi_dphy_power_on()
1263 dw_mipi_dsi_phy_write(dsi, 0x0, 0); in dw_mipi_dsi_dphy_power_on()
1265 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1266 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1271 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1273 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1275 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1277 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1283 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_power_off() local
1286 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1288 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1292 if (dsi->cdata->dphy_rx_power_off) { in dw_mipi_dsi_dphy_power_off()
1293 ret = dsi->cdata->dphy_rx_power_off(phy); in dw_mipi_dsi_dphy_power_off()
1295 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1298 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1299 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_off()
1301 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_off()
1316 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_resume() local
1323 if (dsi->dsi_bound) { in dw_mipi_dsi_rockchip_resume()
1324 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1326 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_resume()
1330 dw_mipi_dsi_rockchip_config(dsi); in dw_mipi_dsi_rockchip_resume()
1331 if (dsi->slave) in dw_mipi_dsi_rockchip_resume()
1332 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_resume()
1334 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1348 struct dw_mipi_dsi_rockchip *dsi; in dw_mipi_dsi_rockchip_probe() local
1355 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); in dw_mipi_dsi_rockchip_probe()
1356 if (!dsi) in dw_mipi_dsi_rockchip_probe()
1360 dsi->base = devm_ioremap_resource(dev, res); in dw_mipi_dsi_rockchip_probe()
1361 if (IS_ERR(dsi->base)) { in dw_mipi_dsi_rockchip_probe()
1363 return PTR_ERR(dsi->base); in dw_mipi_dsi_rockchip_probe()
1369 dsi->cdata = &cdata[i]; in dw_mipi_dsi_rockchip_probe()
1376 if (!dsi->cdata) { in dw_mipi_dsi_rockchip_probe()
1382 dsi->phy = devm_phy_optional_get(dev, "dphy"); in dw_mipi_dsi_rockchip_probe()
1383 if (IS_ERR(dsi->phy)) { in dw_mipi_dsi_rockchip_probe()
1384 ret = PTR_ERR(dsi->phy); in dw_mipi_dsi_rockchip_probe()
1389 dsi->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi_rockchip_probe()
1390 if (IS_ERR(dsi->pclk)) { in dw_mipi_dsi_rockchip_probe()
1391 ret = PTR_ERR(dsi->pclk); in dw_mipi_dsi_rockchip_probe()
1396 dsi->pllref_clk = devm_clk_get(dev, "ref"); in dw_mipi_dsi_rockchip_probe()
1397 if (IS_ERR(dsi->pllref_clk)) { in dw_mipi_dsi_rockchip_probe()
1398 if (dsi->phy) { in dw_mipi_dsi_rockchip_probe()
1403 dsi->pllref_clk = NULL; in dw_mipi_dsi_rockchip_probe()
1405 ret = PTR_ERR(dsi->pllref_clk); in dw_mipi_dsi_rockchip_probe()
1413 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { in dw_mipi_dsi_rockchip_probe()
1414 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); in dw_mipi_dsi_rockchip_probe()
1415 if (IS_ERR(dsi->phy_cfg_clk)) { in dw_mipi_dsi_rockchip_probe()
1416 ret = PTR_ERR(dsi->phy_cfg_clk); in dw_mipi_dsi_rockchip_probe()
1423 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { in dw_mipi_dsi_rockchip_probe()
1424 dsi->grf_clk = devm_clk_get(dev, "grf"); in dw_mipi_dsi_rockchip_probe()
1425 if (IS_ERR(dsi->grf_clk)) { in dw_mipi_dsi_rockchip_probe()
1426 ret = PTR_ERR(dsi->grf_clk); in dw_mipi_dsi_rockchip_probe()
1432 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in dw_mipi_dsi_rockchip_probe()
1433 if (IS_ERR(dsi->grf_regmap)) { in dw_mipi_dsi_rockchip_probe()
1435 return PTR_ERR(dsi->grf_regmap); in dw_mipi_dsi_rockchip_probe()
1438 dsi->dev = dev; in dw_mipi_dsi_rockchip_probe()
1439 dsi->pdata.base = dsi->base; in dw_mipi_dsi_rockchip_probe()
1440 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; in dw_mipi_dsi_rockchip_probe()
1441 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; in dw_mipi_dsi_rockchip_probe()
1442 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; in dw_mipi_dsi_rockchip_probe()
1443 dsi->pdata.priv_data = dsi; in dw_mipi_dsi_rockchip_probe()
1444 platform_set_drvdata(pdev, dsi); in dw_mipi_dsi_rockchip_probe()
1446 mutex_init(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_probe()
1448 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); in dw_mipi_dsi_rockchip_probe()
1449 if (IS_ERR(dsi->dphy)) { in dw_mipi_dsi_rockchip_probe()
1451 return PTR_ERR(dsi->dphy); in dw_mipi_dsi_rockchip_probe()
1454 phy_set_drvdata(dsi->dphy, dsi); in dw_mipi_dsi_rockchip_probe()
1459 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); in dw_mipi_dsi_rockchip_probe()
1460 if (IS_ERR(dsi->dmd)) { in dw_mipi_dsi_rockchip_probe()
1461 ret = PTR_ERR(dsi->dmd); in dw_mipi_dsi_rockchip_probe()
1473 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); in dw_mipi_dsi_rockchip_remove() local
1475 dw_mipi_dsi_remove(dsi->dmd); in dw_mipi_dsi_rockchip_remove()
1520 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_init() local
1526 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1528 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1530 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1532 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_init()
1540 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_power_on() local
1543 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); in rk3399_dphy_tx1rx1_power_on()
1546 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1548 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1551 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1553 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1557 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1559 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1564 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in rk3399_dphy_tx1rx1_power_on()
1568 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1569 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), in rk3399_dphy_tx1rx1_power_on()
1579 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_power_off() local
1581 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_off()