Lines Matching refs:bclk
42 unsigned long bclk; member
591 unsigned long delay, bclk, bclk_ganged; in tegra_dsi_configure() local
600 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); in tegra_dsi_configure()
601 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); in tegra_dsi_configure()
602 value = bclk - bclk_ganged + delay + 20; in tegra_dsi_configure()
704 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, in tegra_dsi_set_timeout() argument
711 timeout = (bclk / vrefresh) / 512; in tegra_dsi_set_timeout()
716 timeout = 2 * bclk / 512 * 1000; in tegra_dsi_set_timeout()
724 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); in tegra_dsi_set_timeout()
923 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh); in tegra_dsi_encoder_enable()
978 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); in tegra_dsi_encoder_atomic_check()
984 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk); in tegra_dsi_encoder_atomic_check()
989 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC; in tegra_dsi_encoder_atomic_check()