Lines Matching refs:hw_plane
324 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) in dispc_vid_write() argument
326 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
331 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) in dispc_vid_read() argument
333 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
405 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, in VID_REG_GET() argument
408 return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end); in VID_REG_GET()
411 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx, in VID_REG_FLD_MOD() argument
414 dispc_vid_write(dispc, hw_plane, idx, in VID_REG_FLD_MOD()
415 FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), in VID_REG_FLD_MOD()
479 static dispc_irq_t dispc_vid_irq_from_raw(u32 stat, u32 hw_plane) in dispc_vid_irq_from_raw() argument
484 vid_stat |= DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane); in dispc_vid_irq_from_raw()
489 static u32 dispc_vid_irq_to_raw(dispc_irq_t vidstat, u32 hw_plane) in dispc_vid_irq_to_raw() argument
493 if (vidstat & DSS_IRQ_PLANE_FIFO_UNDERFLOW(hw_plane)) in dispc_vid_irq_to_raw()
516 u32 hw_plane) in dispc_k2g_vid_read_irqstatus() argument
518 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS); in dispc_k2g_vid_read_irqstatus()
520 return dispc_vid_irq_from_raw(stat, hw_plane); in dispc_k2g_vid_read_irqstatus()
524 u32 hw_plane, dispc_irq_t vidstat) in dispc_k2g_vid_write_irqstatus() argument
526 u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane); in dispc_k2g_vid_write_irqstatus()
528 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat); in dispc_k2g_vid_write_irqstatus()
548 u32 hw_plane) in dispc_k2g_vid_read_irqenable() argument
550 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE); in dispc_k2g_vid_read_irqenable()
552 return dispc_vid_irq_from_raw(stat, hw_plane); in dispc_k2g_vid_read_irqenable()
556 u32 hw_plane, dispc_irq_t vidstat) in dispc_k2g_vid_set_irqenable() argument
558 u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane); in dispc_k2g_vid_set_irqenable()
560 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat); in dispc_k2g_vid_set_irqenable()
631 u32 hw_plane) in dispc_k3_vid_read_irqstatus() argument
633 u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane)); in dispc_k3_vid_read_irqstatus()
635 return dispc_vid_irq_from_raw(stat, hw_plane); in dispc_k3_vid_read_irqstatus()
639 u32 hw_plane, dispc_irq_t vidstat) in dispc_k3_vid_write_irqstatus() argument
641 u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane); in dispc_k3_vid_write_irqstatus()
643 dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat); in dispc_k3_vid_write_irqstatus()
663 u32 hw_plane) in dispc_k3_vid_read_irqenable() argument
665 u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane)); in dispc_k3_vid_read_irqenable()
667 return dispc_vid_irq_from_raw(stat, hw_plane); in dispc_k3_vid_read_irqenable()
671 u32 hw_plane, dispc_irq_t vidstat) in dispc_k3_vid_set_irqenable() argument
673 u32 stat = dispc_vid_irq_to_raw(vidstat, hw_plane); in dispc_k3_vid_set_irqenable()
675 dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat); in dispc_k3_vid_set_irqenable()
1244 u32 hw_plane, u32 hw_videoport, in dispc_k2g_ovr_set_plane() argument
1248 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION, in dispc_k2g_ovr_set_plane()
1253 u32 hw_plane, u32 hw_videoport, in dispc_am65x_ovr_set_plane() argument
1257 hw_plane, 4, 1); in dispc_am65x_ovr_set_plane()
1265 u32 hw_plane, u32 hw_videoport, in dispc_j721e_ovr_set_plane() argument
1269 hw_plane, 4, 1); in dispc_j721e_ovr_set_plane()
1276 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, in dispc_ovr_set_plane() argument
1281 dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport, in dispc_ovr_set_plane()
1285 dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, in dispc_ovr_set_plane()
1289 dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport, in dispc_ovr_set_plane()
1387 static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, in dispc_k2g_vid_write_csc() argument
1406 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i], in dispc_k2g_vid_write_csc()
1410 static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, in dispc_k3_vid_write_csc() argument
1425 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i], in dispc_k3_vid_write_csc()
1507 static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane, in dispc_vid_csc_setup() argument
1520 dispc_k2g_vid_write_csc(dispc, hw_plane, coef); in dispc_vid_csc_setup()
1522 dispc_k3_vid_write_csc(dispc, hw_plane, coef); in dispc_vid_csc_setup()
1525 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, in dispc_vid_csc_enable() argument
1528 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9); in dispc_vid_csc_enable()
1546 u32 hw_plane, in dispc_vid_write_fir_coefs() argument
1577 dispc_vid_write(dispc, hw_plane, reg, c0); in dispc_vid_write_fir_coefs()
1589 dispc_vid_write(dispc, hw_plane, reg, c12); in dispc_vid_write_fir_coefs()
1779 u32 hw_plane, in dispc_vid_set_scaling() argument
1784 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_vid_set_scaling()
1788 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_vid_set_scaling()
1796 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_vid_set_scaling()
1801 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, in dispc_vid_set_scaling()
1803 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1808 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2, in dispc_vid_set_scaling()
1810 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1817 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc); in dispc_vid_set_scaling()
1818 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1824 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc); in dispc_vid_set_scaling()
1825 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1879 u32 hw_plane, u32 fourcc) in dispc_plane_set_pixel_format() argument
1885 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_plane_set_pixel_format()
1917 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, in dispc_plane_check() argument
1921 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_check()
1934 state->color_range, hw_plane); in dispc_plane_check()
1943 __func__, hw_plane, in dispc_plane_check()
1988 int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, in dispc_plane_setup() argument
1992 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_setup()
2001 dispc_plane_set_pixel_format(dispc, hw_plane, fourcc); in dispc_plane_setup()
2003 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff); in dispc_plane_setup()
2004 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32); in dispc_plane_setup()
2005 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff); in dispc_plane_setup()
2006 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32); in dispc_plane_setup()
2008 dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE, in dispc_plane_setup()
2013 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, in dispc_plane_setup()
2016 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, in dispc_plane_setup()
2019 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC, in dispc_plane_setup()
2029 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2031 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2033 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2035 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2038 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV, in dispc_plane_setup()
2045 dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE, in dispc_plane_setup()
2049 dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc); in dispc_plane_setup()
2054 dispc_vid_csc_setup(dispc, hw_plane, state); in dispc_plane_setup()
2055 dispc_vid_csc_enable(dispc, hw_plane, true); in dispc_plane_setup()
2057 dispc_vid_csc_enable(dispc, hw_plane, false); in dispc_plane_setup()
2060 dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, in dispc_plane_setup()
2064 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, in dispc_plane_setup()
2067 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, in dispc_plane_setup()
2073 int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) in dispc_plane_enable() argument
2075 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); in dispc_plane_enable()
2080 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane) in dispc_vid_get_fifo_size() argument
2082 return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0); in dispc_vid_get_fifo_size()
2086 u32 hw_plane, u32 low, u32 high) in dispc_vid_set_mflag_threshold() argument
2088 dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, in dispc_vid_set_mflag_threshold()
2093 u32 hw_plane, u32 low, u32 high) in dispc_vid_set_buf_threshold() argument
2095 dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD, in dispc_vid_set_buf_threshold()
2101 unsigned int hw_plane; in dispc_k2g_plane_init() local
2110 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k2g_plane_init()
2111 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); in dispc_k2g_plane_init()
2126 dispc->feat->vid_name[hw_plane], in dispc_k2g_plane_init()
2132 dispc_vid_set_buf_threshold(dispc, hw_plane, in dispc_k2g_plane_init()
2134 dispc_vid_set_mflag_threshold(dispc, hw_plane, in dispc_k2g_plane_init()
2137 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); in dispc_k2g_plane_init()
2144 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, in dispc_k2g_plane_init()
2151 unsigned int hw_plane; in dispc_k3_plane_init() local
2165 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k3_plane_init()
2166 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); in dispc_k3_plane_init()
2181 dispc->feat->vid_name[hw_plane], in dispc_k3_plane_init()
2187 dispc_vid_set_buf_threshold(dispc, hw_plane, in dispc_k3_plane_init()
2189 dispc_vid_set_mflag_threshold(dispc, hw_plane, in dispc_k3_plane_init()
2192 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); in dispc_k3_plane_init()
2195 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, in dispc_k3_plane_init()