Lines Matching refs:VC4_SET_FIELD
278 ret |= VC4_SET_FIELD((level >> 6), in vc4_crtc_get_fifo_full_level_bits()
281 return ret | VC4_SET_FIELD(level & 0x3f, in vc4_crtc_get_fifo_full_level_bits()
362 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, in vc4_crtc_config_pv()
364 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, in vc4_crtc_config_pv()
368 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, in vc4_crtc_config_pv()
370 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, in vc4_crtc_config_pv()
394 VC4_SET_FIELD(vert_bp_even, PV_VERTA_VBP) | in vc4_crtc_config_pv()
395 VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC)); in vc4_crtc_config_pv()
397 VC4_SET_FIELD(vert_fp_even, PV_VERTB_VFP) | in vc4_crtc_config_pv()
398 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); in vc4_crtc_config_pv()
409 : VC4_SET_FIELD(field_delay, in vc4_crtc_config_pv()
421 VC4_SET_FIELD(vert_bp, PV_VERTA_VBP) | in vc4_crtc_config_pv()
422 VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC)); in vc4_crtc_config_pv()
424 VC4_SET_FIELD(vert_fp, PV_VERTB_VFP) | in vc4_crtc_config_pv()
425 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); in vc4_crtc_config_pv()
432 VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP, in vc4_crtc_config_pv()
437 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | in vc4_crtc_config_pv()
438 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | in vc4_crtc_config_pv()
442 VC4_SET_FIELD(vc4_encoder->clock_select, in vc4_crtc_config_pv()