Lines Matching refs:VC4_SET_FIELD
947 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_bridge_pre_enable()
948 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ)); in vc4_dsi_bridge_pre_enable()
962 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) | in vc4_dsi_bridge_pre_enable()
963 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) | in vc4_dsi_bridge_pre_enable()
964 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE)); in vc4_dsi_bridge_pre_enable()
966 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_bridge_pre_enable()
967 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) | in vc4_dsi_bridge_pre_enable()
968 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) | in vc4_dsi_bridge_pre_enable()
969 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) | in vc4_dsi_bridge_pre_enable()
970 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) | in vc4_dsi_bridge_pre_enable()
971 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) | in vc4_dsi_bridge_pre_enable()
972 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3)); in vc4_dsi_bridge_pre_enable()
1031 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0), in vc4_dsi_bridge_pre_enable()
1033 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8), in vc4_dsi_bridge_pre_enable()
1035 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0), in vc4_dsi_bridge_pre_enable()
1039 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0), in vc4_dsi_bridge_pre_enable()
1041 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52), in vc4_dsi_bridge_pre_enable()
1045 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0), in vc4_dsi_bridge_pre_enable()
1049 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0), in vc4_dsi_bridge_pre_enable()
1051 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6), in vc4_dsi_bridge_pre_enable()
1053 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4), in vc4_dsi_bridge_pre_enable()
1057 VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0), in vc4_dsi_bridge_pre_enable()
1059 VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8), in vc4_dsi_bridge_pre_enable()
1062 VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT)); in vc4_dsi_bridge_pre_enable()
1073 DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, in vc4_dsi_bridge_pre_enable()
1078 VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) | in vc4_dsi_bridge_pre_enable()
1079 VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) | in vc4_dsi_bridge_pre_enable()
1080 VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) | in vc4_dsi_bridge_pre_enable()
1081 VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX)); in vc4_dsi_bridge_pre_enable()
1084 VC4_SET_FIELD(dsi_esc_timing(1000000), in vc4_dsi_bridge_pre_enable()
1096 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) : in vc4_dsi_bridge_pre_enable()
1097 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT))); in vc4_dsi_bridge_pre_enable()
1116 VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE, in vc4_dsi_bridge_pre_enable()
1135 VC4_SET_FIELD(dsi->divider, in vc4_dsi_bridge_pre_enable()
1137 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | in vc4_dsi_bridge_pre_enable()
1138 VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME, in vc4_dsi_bridge_pre_enable()
1187 pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT); in vc4_dsi_host_transfer()
1188 pkth |= VC4_SET_FIELD(packet.header[1] | in vc4_dsi_host_transfer()
1213 pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO); in vc4_dsi_host_transfer()
1217 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX, in vc4_dsi_host_transfer()
1220 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX, in vc4_dsi_host_transfer()
1244 pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT); in vc4_dsi_host_transfer()
1248 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY, in vc4_dsi_host_transfer()
1251 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT, in vc4_dsi_host_transfer()
1267 VC4_SET_FIELD(DSI0_INT_CMDC_DONE_NO_REPEAT, in vc4_dsi_host_transfer()