Lines Matching refs:dsi
618 dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val) in dsi_dma_workaround_write() argument
620 struct dma_chan *chan = dsi->reg_dma_chan; in dsi_dma_workaround_write()
629 writel(val, dsi->regs + offset); in dsi_dma_workaround_write()
633 *dsi->reg_dma_mem = val; in dsi_dma_workaround_write()
636 dsi->reg_paddr + offset, in dsi_dma_workaround_write()
637 dsi->reg_dma_paddr, in dsi_dma_workaround_write()
658 readl(dsi->regs + (offset)); \
661 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
663 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
665 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
666 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
718 static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch) in vc4_dsi_latch_ulps() argument
731 static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps) in vc4_dsi_ulps() argument
733 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS; in vc4_dsi_ulps()
736 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | in vc4_dsi_ulps()
737 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | in vc4_dsi_ulps()
738 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); in vc4_dsi_ulps()
741 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | in vc4_dsi_ulps()
742 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | in vc4_dsi_ulps()
743 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); in vc4_dsi_ulps()
746 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | in vc4_dsi_ulps()
747 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | in vc4_dsi_ulps()
748 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); in vc4_dsi_ulps()
760 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
764 vc4_dsi_latch_ulps(dsi, false); in vc4_dsi_ulps()
773 vc4_dsi_latch_ulps(dsi, ulps); in vc4_dsi_ulps()
779 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
808 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); in vc4_dsi_bridge_disable() local
819 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); in vc4_dsi_bridge_post_disable() local
820 struct device *dev = &dsi->pdev->dev; in vc4_dsi_bridge_post_disable()
822 clk_disable_unprepare(dsi->pll_phy_clock); in vc4_dsi_bridge_post_disable()
823 clk_disable_unprepare(dsi->escape_clock); in vc4_dsi_bridge_post_disable()
824 clk_disable_unprepare(dsi->pixel_clock); in vc4_dsi_bridge_post_disable()
846 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); in vc4_dsi_bridge_mode_fixup() local
847 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock); in vc4_dsi_bridge_mode_fixup()
850 unsigned long pll_clock = pixel_clock_hz * dsi->divider; in vc4_dsi_bridge_mode_fixup()
865 pixel_clock_hz = pll_clock / dsi->divider; in vc4_dsi_bridge_mode_fixup()
882 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); in vc4_dsi_bridge_pre_enable() local
884 struct device *dev = &dsi->pdev->dev; in vc4_dsi_bridge_pre_enable()
900 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port); in vc4_dsi_bridge_pre_enable()
905 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_bridge_pre_enable()
906 dev_info(&dsi->pdev->dev, "DSI regs before:\n"); in vc4_dsi_bridge_pre_enable()
907 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_bridge_pre_enable()
926 phy_clock = (pixel_clock_hz + 1000) * dsi->divider; in vc4_dsi_bridge_pre_enable()
927 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); in vc4_dsi_bridge_pre_enable()
929 dev_err(&dsi->pdev->dev, in vc4_dsi_bridge_pre_enable()
946 if (dsi->variant->port == 0) { in vc4_dsi_bridge_pre_enable()
950 if (dsi->lanes < 2) in vc4_dsi_bridge_pre_enable()
953 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) in vc4_dsi_bridge_pre_enable()
974 if (dsi->lanes < 4) in vc4_dsi_bridge_pre_enable()
976 if (dsi->lanes < 3) in vc4_dsi_bridge_pre_enable()
978 if (dsi->lanes < 2) in vc4_dsi_bridge_pre_enable()
991 ret = clk_prepare_enable(dsi->escape_clock); in vc4_dsi_bridge_pre_enable()
997 ret = clk_prepare_enable(dsi->pll_phy_clock); in vc4_dsi_bridge_pre_enable()
1003 hs_clock = clk_get_rate(dsi->pll_phy_clock); in vc4_dsi_bridge_pre_enable()
1013 ret = clk_set_rate(dsi->pixel_clock, dsip_clock); in vc4_dsi_bridge_pre_enable()
1019 ret = clk_prepare_enable(dsi->pixel_clock); in vc4_dsi_bridge_pre_enable()
1089 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | in vc4_dsi_bridge_pre_enable()
1090 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | in vc4_dsi_bridge_pre_enable()
1091 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | in vc4_dsi_bridge_pre_enable()
1093 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? in vc4_dsi_bridge_pre_enable()
1095 (dsi->variant->port == 0 ? in vc4_dsi_bridge_pre_enable()
1121 if (dsi->variant->port == 0) in vc4_dsi_bridge_pre_enable()
1131 vc4_dsi_ulps(dsi, false); in vc4_dsi_bridge_pre_enable()
1133 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { in vc4_dsi_bridge_pre_enable()
1135 VC4_SET_FIELD(dsi->divider, in vc4_dsi_bridge_pre_enable()
1137 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | in vc4_dsi_bridge_pre_enable()
1150 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); in vc4_dsi_bridge_enable() local
1159 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_bridge_enable()
1160 dev_info(&dsi->pdev->dev, "DSI regs after:\n"); in vc4_dsi_bridge_enable()
1161 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_bridge_enable()
1168 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); in vc4_dsi_bridge_attach() local
1171 return drm_bridge_attach(bridge->encoder, dsi->out_bridge, in vc4_dsi_bridge_attach()
1172 &dsi->bridge, flags); in vc4_dsi_bridge_attach()
1178 struct vc4_dsi *dsi = host_to_dsi(host); in vc4_dsi_host_transfer() local
1256 dsi->xfer_result = 0; in vc4_dsi_host_transfer()
1257 reinit_completion(&dsi->xfer_completion); in vc4_dsi_host_transfer()
1258 if (dsi->variant->port == 0) { in vc4_dsi_host_transfer()
1286 if (!wait_for_completion_timeout(&dsi->xfer_completion, in vc4_dsi_host_transfer()
1288 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); in vc4_dsi_host_transfer()
1289 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n", in vc4_dsi_host_transfer()
1293 ret = dsi->xfer_result; in vc4_dsi_host_transfer()
1350 struct vc4_dsi *dsi = host_to_dsi(host); in vc4_dsi_host_attach() local
1353 dsi->lanes = device->lanes; in vc4_dsi_host_attach()
1354 dsi->channel = device->channel; in vc4_dsi_host_attach()
1355 dsi->mode_flags = device->mode_flags; in vc4_dsi_host_attach()
1359 dsi->format = DSI_PFORMAT_RGB888; in vc4_dsi_host_attach()
1360 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1363 dsi->format = DSI_PFORMAT_RGB666; in vc4_dsi_host_attach()
1364 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1367 dsi->format = DSI_PFORMAT_RGB666_PACKED; in vc4_dsi_host_attach()
1368 dsi->divider = 18 / dsi->lanes; in vc4_dsi_host_attach()
1371 dsi->format = DSI_PFORMAT_RGB565; in vc4_dsi_host_attach()
1372 dsi->divider = 16 / dsi->lanes; in vc4_dsi_host_attach()
1375 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n", in vc4_dsi_host_attach()
1376 dsi->format); in vc4_dsi_host_attach()
1380 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { in vc4_dsi_host_attach()
1381 dev_err(&dsi->pdev->dev, in vc4_dsi_host_attach()
1386 drm_bridge_add(&dsi->bridge); in vc4_dsi_host_attach()
1388 ret = component_add(&dsi->pdev->dev, &vc4_dsi_ops); in vc4_dsi_host_attach()
1390 drm_bridge_remove(&dsi->bridge); in vc4_dsi_host_attach()
1400 struct vc4_dsi *dsi = host_to_dsi(host); in vc4_dsi_host_detach() local
1402 component_del(&dsi->pdev->dev, &vc4_dsi_ops); in vc4_dsi_host_detach()
1403 drm_bridge_remove(&dsi->bridge); in vc4_dsi_host_detach()
1428 struct vc4_dsi *dsi = to_vc4_dsi(encoder); in vc4_dsi_late_register() local
1430 vc4_debugfs_add_regset32(drm, dsi->variant->debugfs_name, &dsi->regset); in vc4_dsi_late_register()
1468 static void dsi_handle_error(struct vc4_dsi *dsi, in dsi_handle_error() argument
1475 DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type); in dsi_handle_error()
1487 struct vc4_dsi *dsi = data; in vc4_dsi_irq_defer_to_thread_handler() local
1502 struct vc4_dsi *dsi = data; in vc4_dsi_irq_handler() local
1508 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1510 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1512 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1514 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1516 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1518 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1520 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1522 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1525 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE : in vc4_dsi_irq_handler()
1528 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1531 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1532 dsi->xfer_result = -ETIMEDOUT; in vc4_dsi_irq_handler()
1545 vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi) in vc4_dsi_init_phy_clocks() argument
1547 struct device *dev = &dsi->pdev->dev; in vc4_dsi_init_phy_clocks()
1548 const char *parent_name = __clk_get_name(dsi->pll_phy_clock); in vc4_dsi_init_phy_clocks()
1559 dsi->clk_onecell = devm_kzalloc(dev, in vc4_dsi_init_phy_clocks()
1560 sizeof(*dsi->clk_onecell) + in vc4_dsi_init_phy_clocks()
1564 if (!dsi->clk_onecell) in vc4_dsi_init_phy_clocks()
1566 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks); in vc4_dsi_init_phy_clocks()
1569 struct clk_fixed_factor *fix = &dsi->phy_clocks[i]; in vc4_dsi_init_phy_clocks()
1575 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name); in vc4_dsi_init_phy_clocks()
1600 dsi->clk_onecell->hws[i] = &fix->hw; in vc4_dsi_init_phy_clocks()
1605 dsi->clk_onecell); in vc4_dsi_init_phy_clocks()
1610 struct vc4_dsi *dsi = ptr; in vc4_dsi_dma_mem_release() local
1611 struct device *dev = &dsi->pdev->dev; in vc4_dsi_dma_mem_release()
1613 dma_free_coherent(dev, 4, dsi->reg_dma_mem, dsi->reg_dma_paddr); in vc4_dsi_dma_mem_release()
1614 dsi->reg_dma_mem = NULL; in vc4_dsi_dma_mem_release()
1619 struct vc4_dsi *dsi = ptr; in vc4_dsi_dma_chan_release() local
1621 dma_release_channel(dsi->reg_dma_chan); in vc4_dsi_dma_chan_release()
1622 dsi->reg_dma_chan = NULL; in vc4_dsi_dma_chan_release()
1627 struct vc4_dsi *dsi = in vc4_dsi_release() local
1630 kfree(dsi); in vc4_dsi_release()
1633 static void vc4_dsi_get(struct vc4_dsi *dsi) in vc4_dsi_get() argument
1635 kref_get(&dsi->kref); in vc4_dsi_get()
1638 static void vc4_dsi_put(struct vc4_dsi *dsi) in vc4_dsi_put() argument
1640 kref_put(&dsi->kref, &vc4_dsi_release); in vc4_dsi_put()
1645 struct vc4_dsi *dsi = ptr; in vc4_dsi_release_action() local
1647 vc4_dsi_put(dsi); in vc4_dsi_release_action()
1654 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_bind() local
1655 struct drm_encoder *encoder = &dsi->encoder.base; in vc4_dsi_bind()
1658 vc4_dsi_get(dsi); in vc4_dsi_bind()
1660 ret = drmm_add_action_or_reset(drm, vc4_dsi_release_action, dsi); in vc4_dsi_bind()
1664 dsi->variant = of_device_get_match_data(dev); in vc4_dsi_bind()
1666 dsi->encoder.type = dsi->variant->port ? in vc4_dsi_bind()
1669 dsi->regs = vc4_ioremap_regs(pdev, 0); in vc4_dsi_bind()
1670 if (IS_ERR(dsi->regs)) in vc4_dsi_bind()
1671 return PTR_ERR(dsi->regs); in vc4_dsi_bind()
1673 dsi->regset.base = dsi->regs; in vc4_dsi_bind()
1674 dsi->regset.regs = dsi->variant->regs; in vc4_dsi_bind()
1675 dsi->regset.nregs = dsi->variant->nregs; in vc4_dsi_bind()
1687 if (dsi->variant->broken_axi_workaround) { in vc4_dsi_bind()
1690 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4, in vc4_dsi_bind()
1691 &dsi->reg_dma_paddr, in vc4_dsi_bind()
1693 if (!dsi->reg_dma_mem) { in vc4_dsi_bind()
1698 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_mem_release, dsi); in vc4_dsi_bind()
1705 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask); in vc4_dsi_bind()
1706 if (IS_ERR(dsi->reg_dma_chan)) { in vc4_dsi_bind()
1707 ret = PTR_ERR(dsi->reg_dma_chan); in vc4_dsi_bind()
1714 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_chan_release, dsi); in vc4_dsi_bind()
1722 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node, in vc4_dsi_bind()
1726 init_completion(&dsi->xfer_completion); in vc4_dsi_bind()
1732 if (dsi->reg_dma_mem) in vc4_dsi_bind()
1737 "vc4 dsi", dsi); in vc4_dsi_bind()
1740 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi); in vc4_dsi_bind()
1747 dsi->escape_clock = devm_clk_get(dev, "escape"); in vc4_dsi_bind()
1748 if (IS_ERR(dsi->escape_clock)) { in vc4_dsi_bind()
1749 ret = PTR_ERR(dsi->escape_clock); in vc4_dsi_bind()
1755 dsi->pll_phy_clock = devm_clk_get(dev, "phy"); in vc4_dsi_bind()
1756 if (IS_ERR(dsi->pll_phy_clock)) { in vc4_dsi_bind()
1757 ret = PTR_ERR(dsi->pll_phy_clock); in vc4_dsi_bind()
1763 dsi->pixel_clock = devm_clk_get(dev, "pixel"); in vc4_dsi_bind()
1764 if (IS_ERR(dsi->pixel_clock)) { in vc4_dsi_bind()
1765 ret = PTR_ERR(dsi->pixel_clock); in vc4_dsi_bind()
1771 dsi->out_bridge = drmm_of_get_bridge(drm, dev->of_node, 0, 0); in vc4_dsi_bind()
1772 if (IS_ERR(dsi->out_bridge)) in vc4_dsi_bind()
1773 return PTR_ERR(dsi->out_bridge); in vc4_dsi_bind()
1776 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000); in vc4_dsi_bind()
1782 ret = vc4_dsi_init_phy_clocks(dsi); in vc4_dsi_bind()
1797 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0); in vc4_dsi_bind()
1811 struct vc4_dsi *dsi; in vc4_dsi_dev_probe() local
1813 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL); in vc4_dsi_dev_probe()
1814 if (!dsi) in vc4_dsi_dev_probe()
1816 dev_set_drvdata(dev, dsi); in vc4_dsi_dev_probe()
1818 kref_init(&dsi->kref); in vc4_dsi_dev_probe()
1820 dsi->pdev = pdev; in vc4_dsi_dev_probe()
1821 dsi->bridge.funcs = &vc4_dsi_bridge_funcs; in vc4_dsi_dev_probe()
1823 dsi->bridge.of_node = dev->of_node; in vc4_dsi_dev_probe()
1825 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; in vc4_dsi_dev_probe()
1826 dsi->dsi_host.ops = &vc4_dsi_host_ops; in vc4_dsi_dev_probe()
1827 dsi->dsi_host.dev = dev; in vc4_dsi_dev_probe()
1828 mipi_dsi_host_register(&dsi->dsi_host); in vc4_dsi_dev_probe()
1836 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_dev_remove() local
1838 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_dev_remove()
1839 vc4_dsi_put(dsi); in vc4_dsi_dev_remove()