Lines Matching refs:pixel_rep
1240 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; in vc4_hdmi_set_timings() local
1266 VC4_SET_FIELD(mode->hdisplay * pixel_rep, in vc4_hdmi_set_timings()
1271 mode->hsync_end) * pixel_rep, in vc4_hdmi_set_timings()
1274 mode->hsync_start) * pixel_rep, in vc4_hdmi_set_timings()
1277 mode->hdisplay) * pixel_rep, in vc4_hdmi_set_timings()
1288 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); in vc4_hdmi_set_timings()
1306 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; in vc5_hdmi_set_timings() local
1312 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), in vc5_hdmi_set_timings()
1334 VC4_SET_FIELD(mode->hdisplay * pixel_rep, in vc5_hdmi_set_timings()
1337 mode->hdisplay) * pixel_rep, in vc5_hdmi_set_timings()
1342 mode->hsync_end) * pixel_rep, in vc5_hdmi_set_timings()
1345 mode->hsync_start) * pixel_rep, in vc5_hdmi_set_timings()
1395 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); in vc5_hdmi_set_timings()