Lines Matching refs:read_csr
1308 u64 read_csr(const struct hfi1_devdata *dd, u32 offset) in read_csr() function
1356 ret = read_csr(dd, csr); in read_write_csr()
5227 mask = read_csr(rcd->dd, CCE_INT_MASK + (8 * (is / 64))); in is_urg_masked()
5678 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */ in handle_send_egress_err_info()
5679 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO); in handle_send_egress_err_info()
6341 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1); in handle_8051_request()
6369 (void)read_csr(dd, DCC_CFG_RESET); in handle_8051_request()
6396 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); in set_up_vau()
6411 u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); in set_up_vl15()
6484 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN); in lcb_shutdown()
6485 reg = read_csr(dd, DCC_CFG_RESET); in lcb_shutdown()
6488 (void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */ in lcb_shutdown()
6717 rcvctrl = read_csr(dd, RCV_CTRL); in adjust_rcvctrl()
6788 reg = read_csr(dd, CCE_STATUS); in wait_for_freeze_status()
7502 reg = read_csr(dd, SEND_CM_CTRL); in handle_verify_cap()
7565 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN); in handle_verify_cap()
7739 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051); in handle_8051_interrupt()
7844 read_csr(dd, DC_DC8051_ERR_EN) & in handle_8051_interrupt()
7934 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE); in handle_dcc_err()
7953 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG); in handle_dcc_err()
8004 info = read_csr(dd, DCC_ERR_INFO_PORTRCV); in handle_dcc_err()
8005 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0); in handle_dcc_err()
8006 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1); in handle_dcc_err()
8302 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) & in general_interrupt()
8334 status = read_csr(dd, in sdma_interrupt()
8364 (void)read_csr(dd, addr); in clear_recv_intr()
8541 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); in read_physical_state()
8550 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); in read_logical_state()
8559 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); in set_logical_state()
8576 *data = read_csr(dd, addr); in read_lcb_via_8051()
8656 *data = read_csr(dd, addr); in read_lcb_csr()
8768 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0); in do_8051_command()
8792 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1); in do_8051_command()
8812 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1) in do_8051_command()
9269 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK)); in init_loopback()
9486 mask = read_csr(dd, dd->hfi1_id ? in wait_for_qsfp_init()
9504 mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK); in set_qsfp_int_n()
9530 qsfp_mask = read_csr(dd, in reset_qsfp()
10161 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG); in set_send_length()
10174 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1); in set_lidlmc()
10346 reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE); in wait_link_transfer_active()
10377 (void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET); in force_logical_link_state_down()
10649 reg = read_csr(ppd->dd, SEND_CM_CREDIT_VL + (8 * i)); in data_vls_operational()
11175 u64 reg = read_csr(dd, csr); in read_one_cm_vl()
11204 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); in get_buffer_control()
11221 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0); in get_sc2vlnt()
11229 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16); in get_sc2vlnt()
11303 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); in set_global_shared()
11314 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); in set_global_limit()
11331 reg = read_csr(dd, addr); in set_vl_shared()
11348 reg = read_csr(dd, addr); in set_vl_dedicated()
11363 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask; in wait_for_vl_status_clear()
13155 reg = read_csr(dd, ASIC_STS_THERM); in hfi1_tempsense_rd()
13187 reg = read_csr(dd, CCE_INT_MASK + (8 * idx)); in read_mod_write()
13280 reg = read_csr(dd, CCE_INT_MAP + (8 * m)); in remap_intr()
13603 reg = read_csr(dd, CCE_STATUS); in clear_cce_status()
13613 reg = read_csr(dd, CCE_STATUS); in clear_cce_status()
13831 reg = read_csr(dd, RCV_STATUS); in init_rbufs()
13860 read_csr(dd, RCV_CTRL); in init_rbufs()
13867 reg = read_csr(dd, RCV_STATUS); in init_rbufs()
14057 (void)read_csr(dd, CCE_DC_CTRL); in init_chip()
14161 u64 reg = read_csr(dd, RCV_QP_MAP_TABLE + (idx / 8) * 8); in hfi1_get_qp_map()
14269 return read_csr(dd, RCV_RSM_CFG + (8 * rule_index)) != 0; in has_rsm_rule()
14540 reg = read_csr(dd, regoff); in hfi1_netdev_update_rmt()
14557 reg = read_csr(dd, regoff); in hfi1_netdev_update_rmt()
14675 val = read_csr(dd, RCV_BYPASS); in init_rxe()
14960 mask = read_csr(dd, CCE_INT_MASK); in check_int_registers()
14962 reg = read_csr(dd, CCE_INT_MASK); in check_int_registers()
14968 reg = read_csr(dd, CCE_INT_STATUS); in check_int_registers()
14974 reg = read_csr(dd, CCE_INT_STATUS); in check_int_registers()
15091 reg = read_csr(dd, CCE_REVISION2); in hfi1_init_dd()