Lines Matching refs:dd_dev_info
120 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); in hfi1_pcie_ddinit()
130 dd_dev_info(dd, "RcvArray count: %u\n", rcv_array_count); in hfi1_pcie_ddinit()
140 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2, in hfi1_pcie_ddinit()
148 dd_dev_info(dd, "WC piobase: %p for %x\n", dd->piobase, TXE_PIO_SIZE); in hfi1_pcie_ddinit()
162 dd_dev_info(dd, "WC RcvArray: %p for %x\n", in hfi1_pcie_ddinit()
264 dd_dev_info(dd, in pcie_speeds()
276 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); in pcie_speeds()
283 dd_dev_info(dd, "%s\n", dd->lbus_info); in pcie_speeds()
432 dd_dev_info(dd, "Enabling PCIe extended tags\n"); in tune_pcie_caps()
437 dd_dev_info(dd, "Unable to write to PCI config\n"); in tune_pcie_caps()
446 dd_dev_info(dd, "Parent not found\n"); in tune_pcie_caps()
450 dd_dev_info(dd, "Parent not root\n"); in tune_pcie_caps()
454 dd_dev_info(dd, "Parent is not PCI Express capable\n"); in tune_pcie_caps()
458 dd_dev_info(dd, "PCI device is not PCI Express capable\n"); in tune_pcie_caps()
522 dd_dev_info(dd, "State Normal, ignoring\n"); in pci_error_detected()
526 dd_dev_info(dd, "State Frozen, requesting reset\n"); in pci_error_detected()
533 dd_dev_info(dd, "State Permanent Failure, disabling\n"); in pci_error_detected()
543 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", in pci_error_detected()
561 dd_dev_info(dd, in pci_mmio_enabled()
573 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); in pci_slot_reset()
582 dd_dev_info(dd, "HFI1 resume function called\n"); in pci_resume()
978 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); in do_pcie_gen3_transition()
984 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, in do_pcie_gen3_transition()
996 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n", in do_pcie_gen3_transition()
1031 dd_dev_info(dd, "%s: Disabled therm polling\n", in do_pcie_gen3_transition()
1040 dd_dev_info(dd, "%s: downloading firmware\n", __func__); in do_pcie_gen3_transition()
1049 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); in do_pcie_gen3_transition()
1132 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pset); in do_pcie_gen3_transition()
1142 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); in do_pcie_gen3_transition()
1186 dd_dev_info(dd, "%s: clearing ASPM\n", __func__); in do_pcie_gen3_transition()
1205 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); in do_pcie_gen3_transition()
1213 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1219 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1229 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); in do_pcie_gen3_transition()
1232 dd_dev_info(dd, "%s: setting target link speed\n", __func__); in do_pcie_gen3_transition()
1240 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1244 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1260 dd_dev_info(dd, "%s: arming gasket logic\n", __func__); in do_pcie_gen3_transition()
1276 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); in do_pcie_gen3_transition()
1286 dd_dev_info(dd, in do_pcie_gen3_transition()
1293 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); in do_pcie_gen3_transition()
1300 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); in do_pcie_gen3_transition()
1323 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); in do_pcie_gen3_transition()
1345 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); in do_pcie_gen3_transition()
1369 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, in do_pcie_gen3_transition()
1390 dd_dev_info(dd, "%s: Re-enable therm polling\n", in do_pcie_gen3_transition()
1401 dd_dev_info(dd, "%s: done\n", __func__); in do_pcie_gen3_transition()