Lines Matching defs:qib_chip_specific
545 struct qib_chip_specific { struct
546 u64 __iomem *cregbase;
547 u64 *cntrs;
548 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
549 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
550 u64 main_int_mask; /* clear bits which have dedicated handlers */
551 u64 int_enable_mask; /* for per port interrupts in single port mode */
552 u64 errormask;
553 u64 hwerrmask;
554 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
555 u64 gpio_mask; /* shadow the gpio mask register */
556 u64 extctrl; /* shadow the gpio output enable, etc... */
557 u32 ncntrs;
558 u32 nportcntrs;
559 u32 cntrnamelen;
560 u32 portcntrnamelen;
561 u32 numctxts;
562 u32 rcvegrcnt;
563 u32 updthresh; /* current AvailUpdThld */
564 u32 updthresh_dflt; /* default AvailUpdThld */
565 u32 r1;
566 u32 num_msix_entries;
567 u32 sdmabufcnt;
568 u32 lastbuf_for_pio;
569 u32 stay_in_freeze;
570 u32 recovery_ports_initted;
572 u32 dca_ctrl;
573 int rhdr_cpu[18];
574 int sdma_cpu[2];
575 u64 dca_rcvhdr_ctrl[5]; /* B, C, D, E, F */
577 struct qib_msix_entry *msix_entries;
578 unsigned long *sendchkenable;
579 unsigned long *sendgrhchk;
580 unsigned long *sendibchk;
581 u32 rcvavail_timeout[18];
582 char emsgbuf[128]; /* for device error interrupt msg buffer */