Lines Matching refs:smmu
89 static void parse_driver_options(struct arm_smmu_device *smmu) in parse_driver_options() argument
94 if (of_property_read_bool(smmu->dev->of_node, in parse_driver_options()
96 smmu->options |= arm_smmu_options[i].opt; in parse_driver_options()
97 dev_notice(smmu->dev, "option %s\n", in parse_driver_options()
180 static void queue_poll_init(struct arm_smmu_device *smmu, in queue_poll_init() argument
185 qp->wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV); in queue_poll_init()
336 static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) in arm_smmu_get_cmdq() argument
338 return &smmu->cmdq; in arm_smmu_get_cmdq()
341 static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, in arm_smmu_cmdq_build_sync_cmd() argument
352 if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { in arm_smmu_cmdq_build_sync_cmd()
360 static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_skip_err() argument
378 dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, in __arm_smmu_cmdq_skip_err()
383 dev_err(smmu->dev, "retrying command fetch\n"); in __arm_smmu_cmdq_skip_err()
405 dev_err(smmu->dev, "skipping command in error state:\n"); in __arm_smmu_cmdq_skip_err()
407 dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); in __arm_smmu_cmdq_skip_err()
415 static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) in arm_smmu_cmdq_skip_err() argument
417 __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); in arm_smmu_cmdq_skip_err()
581 static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, in arm_smmu_cmdq_poll_until_not_full() argument
586 struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); in arm_smmu_cmdq_poll_until_not_full()
600 queue_poll_init(smmu, &qp); in arm_smmu_cmdq_poll_until_not_full()
616 static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_poll_until_msi() argument
621 struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); in __arm_smmu_cmdq_poll_until_msi()
624 queue_poll_init(smmu, &qp); in __arm_smmu_cmdq_poll_until_msi()
640 static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_poll_until_consumed() argument
644 struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); in __arm_smmu_cmdq_poll_until_consumed()
648 queue_poll_init(smmu, &qp); in __arm_smmu_cmdq_poll_until_consumed()
690 static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, in arm_smmu_cmdq_poll_until_sync() argument
693 if (smmu->options & ARM_SMMU_OPT_MSIPOLL) in arm_smmu_cmdq_poll_until_sync()
694 return __arm_smmu_cmdq_poll_until_msi(smmu, llq); in arm_smmu_cmdq_poll_until_sync()
696 return __arm_smmu_cmdq_poll_until_consumed(smmu, llq); in arm_smmu_cmdq_poll_until_sync()
732 static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, in arm_smmu_cmdq_issue_cmdlist() argument
739 struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); in arm_smmu_cmdq_issue_cmdlist()
753 if (arm_smmu_cmdq_poll_until_not_full(smmu, &llq)) in arm_smmu_cmdq_issue_cmdlist()
754 dev_err_ratelimited(smmu->dev, "CMDQ timeout\n"); in arm_smmu_cmdq_issue_cmdlist()
779 arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, &cmdq->q, prod); in arm_smmu_cmdq_issue_cmdlist()
829 ret = arm_smmu_cmdq_poll_until_sync(smmu, &llq); in arm_smmu_cmdq_issue_cmdlist()
831 dev_err_ratelimited(smmu->dev, in arm_smmu_cmdq_issue_cmdlist()
852 static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_issue_cmd() argument
859 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", in __arm_smmu_cmdq_issue_cmd()
864 return arm_smmu_cmdq_issue_cmdlist(smmu, cmd, 1, sync); in __arm_smmu_cmdq_issue_cmd()
867 static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, in arm_smmu_cmdq_issue_cmd() argument
870 return __arm_smmu_cmdq_issue_cmd(smmu, ent, false); in arm_smmu_cmdq_issue_cmd()
873 static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, in arm_smmu_cmdq_issue_cmd_with_sync() argument
876 return __arm_smmu_cmdq_issue_cmd(smmu, ent, true); in arm_smmu_cmdq_issue_cmd_with_sync()
879 static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, in arm_smmu_cmdq_batch_add() argument
886 arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, false); in arm_smmu_cmdq_batch_add()
892 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", in arm_smmu_cmdq_batch_add()
900 static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, in arm_smmu_cmdq_batch_submit() argument
903 return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, true); in arm_smmu_cmdq_batch_submit()
933 arm_smmu_cmdq_issue_cmd(master->smmu, &cmd); in arm_smmu_page_response()
945 void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) in arm_smmu_tlb_inv_asid() argument
948 .opcode = smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_asid()
953 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_tlb_inv_asid()
963 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_sync_cd() local
978 arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); in arm_smmu_sync_cd()
983 arm_smmu_cmdq_batch_submit(smmu, &cmds); in arm_smmu_sync_cd()
986 static int arm_smmu_alloc_cd_leaf_table(struct arm_smmu_device *smmu, in arm_smmu_alloc_cd_leaf_table() argument
991 l1_desc->l2ptr = dmam_alloc_coherent(smmu->dev, size, in arm_smmu_alloc_cd_leaf_table()
994 dev_warn(smmu->dev, in arm_smmu_alloc_cd_leaf_table()
1017 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_get_cd_ptr() local
1026 if (arm_smmu_alloc_cd_leaf_table(smmu, l1_desc)) in arm_smmu_get_cd_ptr()
1122 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_alloc_cd_tables() local
1128 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || in arm_smmu_alloc_cd_tables()
1139 cdcfg->l1_desc = devm_kcalloc(smmu->dev, cdcfg->num_l1_ents, in arm_smmu_alloc_cd_tables()
1148 cdcfg->cdtab = dmam_alloc_coherent(smmu->dev, l1size, &cdcfg->cdtab_dma, in arm_smmu_alloc_cd_tables()
1151 dev_warn(smmu->dev, "failed to allocate context descriptor\n"); in arm_smmu_alloc_cd_tables()
1160 devm_kfree(smmu->dev, cdcfg->l1_desc); in arm_smmu_alloc_cd_tables()
1170 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_free_cd_tables() local
1180 dmam_free_coherent(smmu->dev, size, in arm_smmu_free_cd_tables()
1184 devm_kfree(smmu->dev, cdcfg->l1_desc); in arm_smmu_free_cd_tables()
1192 dmam_free_coherent(smmu->dev, l1size, cdcfg->cdtab, cdcfg->cdtab_dma); in arm_smmu_free_cd_tables()
1226 static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_sync_ste_for_sid() argument
1236 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_sync_ste_for_sid()
1260 struct arm_smmu_device *smmu = NULL; in arm_smmu_write_strtab_ent() local
1273 smmu = master->smmu; in arm_smmu_write_strtab_ent()
1324 if (smmu) in arm_smmu_write_strtab_ent()
1325 arm_smmu_sync_ste_for_sid(smmu, sid); in arm_smmu_write_strtab_ent()
1330 u64 strw = smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_write_strtab_ent()
1341 if (smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_write_strtab_ent()
1371 arm_smmu_sync_ste_for_sid(smmu, sid); in arm_smmu_write_strtab_ent()
1374 arm_smmu_sync_ste_for_sid(smmu, sid); in arm_smmu_write_strtab_ent()
1377 if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) in arm_smmu_write_strtab_ent()
1378 arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd); in arm_smmu_write_strtab_ent()
1400 static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_init_l2_strtab() argument
1404 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_l2_strtab()
1414 desc->l2ptr = dmam_alloc_coherent(smmu->dev, size, &desc->l2ptr_dma, in arm_smmu_init_l2_strtab()
1417 dev_err(smmu->dev, in arm_smmu_init_l2_strtab()
1429 arm_smmu_find_master(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_find_master() argument
1434 lockdep_assert_held(&smmu->streams_mutex); in arm_smmu_find_master()
1436 node = smmu->streams.rb_node; in arm_smmu_find_master()
1451 static int arm_smmu_handle_evt(struct arm_smmu_device *smmu, u64 *evt) in arm_smmu_handle_evt() argument
1522 mutex_lock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1523 master = arm_smmu_find_master(smmu, sid); in arm_smmu_handle_evt()
1541 mutex_unlock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1548 struct arm_smmu_device *smmu = dev; in arm_smmu_evtq_thread() local
1549 struct arm_smmu_queue *q = &smmu->evtq.q; in arm_smmu_evtq_thread()
1559 ret = arm_smmu_handle_evt(smmu, evt); in arm_smmu_evtq_thread()
1563 dev_info(smmu->dev, "event 0x%02x received:\n", id); in arm_smmu_evtq_thread()
1565 dev_info(smmu->dev, "\t0x%016llx\n", in arm_smmu_evtq_thread()
1576 dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n"); in arm_smmu_evtq_thread()
1585 static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt) in arm_smmu_handle_ppr() argument
1597 dev_info(smmu->dev, "unexpected PRI request received:\n"); in arm_smmu_handle_ppr()
1598 dev_info(smmu->dev, in arm_smmu_handle_ppr()
1619 arm_smmu_cmdq_issue_cmd(smmu, &cmd); in arm_smmu_handle_ppr()
1625 struct arm_smmu_device *smmu = dev; in arm_smmu_priq_thread() local
1626 struct arm_smmu_queue *q = &smmu->priq.q; in arm_smmu_priq_thread()
1632 arm_smmu_handle_ppr(smmu, evt); in arm_smmu_priq_thread()
1635 dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n"); in arm_smmu_priq_thread()
1645 static int arm_smmu_device_disable(struct arm_smmu_device *smmu);
1650 struct arm_smmu_device *smmu = dev; in arm_smmu_gerror_handler() local
1652 gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); in arm_smmu_gerror_handler()
1653 gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1659 dev_warn(smmu->dev, in arm_smmu_gerror_handler()
1664 dev_err(smmu->dev, "device has entered Service Failure Mode!\n"); in arm_smmu_gerror_handler()
1665 arm_smmu_device_disable(smmu); in arm_smmu_gerror_handler()
1669 dev_warn(smmu->dev, "GERROR MSI write aborted\n"); in arm_smmu_gerror_handler()
1672 dev_warn(smmu->dev, "PRIQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1675 dev_warn(smmu->dev, "EVTQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1678 dev_warn(smmu->dev, "CMDQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1681 dev_err(smmu->dev, "PRIQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1684 dev_err(smmu->dev, "EVTQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1687 arm_smmu_cmdq_skip_err(smmu); in arm_smmu_gerror_handler()
1689 writel(gerror, smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1695 struct arm_smmu_device *smmu = dev; in arm_smmu_combined_irq_thread() local
1698 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_combined_irq_thread()
1788 arm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd); in arm_smmu_atc_inv_master()
1791 return arm_smmu_cmdq_batch_submit(master->smmu, &cmds); in arm_smmu_atc_inv_master()
1803 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_atc_inv_domain()
1834 arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); in arm_smmu_atc_inv_domain()
1839 return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds); in arm_smmu_atc_inv_domain()
1846 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_context() local
1857 arm_smmu_tlb_inv_asid(smmu, smmu_domain->s1_cfg.cd.asid); in arm_smmu_tlb_inv_context()
1861 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_tlb_inv_context()
1871 struct arm_smmu_device *smmu = smmu_domain->smmu; in __arm_smmu_tlb_inv_range() local
1879 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
1895 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
1921 arm_smmu_cmdq_batch_add(smmu, &cmds, cmd); in __arm_smmu_tlb_inv_range()
1924 arm_smmu_cmdq_batch_submit(smmu, &cmds); in __arm_smmu_tlb_inv_range()
1938 cmd.opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_domain()
1959 .opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_asid()
2000 return master->smmu->features & ARM_SMMU_FEAT_COHERENCY; in arm_smmu_capable()
2059 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_free() local
2076 arm_smmu_bitmap_free(smmu->vmid_map, cfg->vmid); in arm_smmu_domain_free()
2088 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_finalise_s1() local
2097 XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); in arm_smmu_domain_finalise_s1()
2146 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_finalise_s2() local
2150 vmid = arm_smmu_bitmap_alloc(smmu->vmid_map, smmu->vmid_bits); in arm_smmu_domain_finalise_s2()
2179 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_finalise() local
2187 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) in arm_smmu_domain_finalise()
2189 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_domain_finalise()
2194 ias = (smmu->features & ARM_SMMU_FEAT_VAX) ? 52 : 48; in arm_smmu_domain_finalise()
2196 oas = smmu->ias; in arm_smmu_domain_finalise()
2202 ias = smmu->ias; in arm_smmu_domain_finalise()
2203 oas = smmu->oas; in arm_smmu_domain_finalise()
2212 .pgsize_bitmap = smmu->pgsize_bitmap, in arm_smmu_domain_finalise()
2215 .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENCY, in arm_smmu_domain_finalise()
2217 .iommu_dev = smmu->dev, in arm_smmu_domain_finalise()
2238 static __le64 *arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_get_step_for_sid() argument
2241 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_get_step_for_sid()
2243 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { in arm_smmu_get_step_for_sid()
2263 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_install_ste_for_dev() local
2267 __le64 *step = arm_smmu_get_step_for_sid(smmu, sid); in arm_smmu_install_ste_for_dev()
2283 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_ats_supported() local
2286 if (!(smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_ats_supported()
2299 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_enable_ats() local
2307 stu = __ffs(smmu->pgsize_bitmap); in arm_smmu_enable_ats()
2360 master->smmu->ssid_bits); in arm_smmu_enable_pasid()
2404 struct arm_smmu_device *smmu; in arm_smmu_attach_dev() local
2412 smmu = master->smmu; in arm_smmu_attach_dev()
2428 if (!smmu_domain->smmu) { in arm_smmu_attach_dev()
2429 smmu_domain->smmu = smmu; in arm_smmu_attach_dev()
2432 smmu_domain->smmu = NULL; in arm_smmu_attach_dev()
2435 } else if (smmu_domain->smmu != smmu) { in arm_smmu_attach_dev()
2495 if (smmu_domain->smmu) in arm_smmu_flush_iotlb_all()
2534 static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_sid_in_range() argument
2536 unsigned long limit = smmu->strtab_cfg.num_l1_ents; in arm_smmu_sid_in_range()
2538 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_sid_in_range()
2544 static int arm_smmu_init_sid_strtab(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_init_sid_strtab() argument
2547 if (!arm_smmu_sid_in_range(smmu, sid)) in arm_smmu_init_sid_strtab()
2551 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_init_sid_strtab()
2552 return arm_smmu_init_l2_strtab(smmu, sid); in arm_smmu_init_sid_strtab()
2557 static int arm_smmu_insert_master(struct arm_smmu_device *smmu, in arm_smmu_insert_master() argument
2572 mutex_lock(&smmu->streams_mutex); in arm_smmu_insert_master()
2580 ret = arm_smmu_init_sid_strtab(smmu, sid); in arm_smmu_insert_master()
2585 new_node = &(smmu->streams.rb_node); in arm_smmu_insert_master()
2606 rb_insert_color(&new_stream->node, &smmu->streams); in arm_smmu_insert_master()
2611 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_insert_master()
2614 mutex_unlock(&smmu->streams_mutex); in arm_smmu_insert_master()
2622 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_remove_master() local
2625 if (!smmu || !master->streams) in arm_smmu_remove_master()
2628 mutex_lock(&smmu->streams_mutex); in arm_smmu_remove_master()
2630 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_remove_master()
2631 mutex_unlock(&smmu->streams_mutex); in arm_smmu_remove_master()
2641 struct arm_smmu_device *smmu; in arm_smmu_probe_device() local
2651 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); in arm_smmu_probe_device()
2652 if (!smmu) in arm_smmu_probe_device()
2660 master->smmu = smmu; in arm_smmu_probe_device()
2664 ret = arm_smmu_insert_master(smmu, master); in arm_smmu_probe_device()
2669 master->ssid_bits = min(smmu->ssid_bits, master->ssid_bits); in arm_smmu_probe_device()
2681 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) in arm_smmu_probe_device()
2685 if ((smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_probe_device()
2687 smmu->features & ARM_SMMU_FEAT_STALL_FORCE) in arm_smmu_probe_device()
2690 return &smmu->iommu; in arm_smmu_probe_device()
2703 iopf_queue_remove_device(master->smmu->evtq.iopf, dev); in arm_smmu_release_device()
2733 if (smmu_domain->smmu) in arm_smmu_enable_nesting()
2874 static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, in arm_smmu_init_one_queue() argument
2885 q->base = dmam_alloc_coherent(smmu->dev, qsz, &q->base_dma, in arm_smmu_init_one_queue()
2894 dev_err(smmu->dev, in arm_smmu_init_one_queue()
2901 dev_info(smmu->dev, "allocated %u entries for %s\n", in arm_smmu_init_one_queue()
2917 static int arm_smmu_cmdq_init(struct arm_smmu_device *smmu) in arm_smmu_cmdq_init() argument
2919 struct arm_smmu_cmdq *cmdq = &smmu->cmdq; in arm_smmu_cmdq_init()
2925 cmdq->valid_map = (atomic_long_t *)devm_bitmap_zalloc(smmu->dev, nents, in arm_smmu_cmdq_init()
2933 static int arm_smmu_init_queues(struct arm_smmu_device *smmu) in arm_smmu_init_queues() argument
2938 ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, smmu->base, in arm_smmu_init_queues()
2944 ret = arm_smmu_cmdq_init(smmu); in arm_smmu_init_queues()
2949 ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1, in arm_smmu_init_queues()
2955 if ((smmu->features & ARM_SMMU_FEAT_SVA) && in arm_smmu_init_queues()
2956 (smmu->features & ARM_SMMU_FEAT_STALLS)) { in arm_smmu_init_queues()
2957 smmu->evtq.iopf = iopf_queue_alloc(dev_name(smmu->dev)); in arm_smmu_init_queues()
2958 if (!smmu->evtq.iopf) in arm_smmu_init_queues()
2963 if (!(smmu->features & ARM_SMMU_FEAT_PRI)) in arm_smmu_init_queues()
2966 return arm_smmu_init_one_queue(smmu, &smmu->priq.q, smmu->page1, in arm_smmu_init_queues()
2971 static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu) in arm_smmu_init_l1_strtab() argument
2974 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_l1_strtab()
2975 void *strtab = smmu->strtab_cfg.strtab; in arm_smmu_init_l1_strtab()
2977 cfg->l1_desc = devm_kcalloc(smmu->dev, cfg->num_l1_ents, in arm_smmu_init_l1_strtab()
2990 static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu) in arm_smmu_init_strtab_2lvl() argument
2995 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_2lvl()
2999 size = min(size, smmu->sid_bits - STRTAB_SPLIT); in arm_smmu_init_strtab_2lvl()
3003 if (size < smmu->sid_bits) in arm_smmu_init_strtab_2lvl()
3004 dev_warn(smmu->dev, in arm_smmu_init_strtab_2lvl()
3006 size, smmu->sid_bits); in arm_smmu_init_strtab_2lvl()
3009 strtab = dmam_alloc_coherent(smmu->dev, l1size, &cfg->strtab_dma, in arm_smmu_init_strtab_2lvl()
3012 dev_err(smmu->dev, in arm_smmu_init_strtab_2lvl()
3025 return arm_smmu_init_l1_strtab(smmu); in arm_smmu_init_strtab_2lvl()
3028 static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu) in arm_smmu_init_strtab_linear() argument
3033 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_linear()
3035 size = (1 << smmu->sid_bits) * (STRTAB_STE_DWORDS << 3); in arm_smmu_init_strtab_linear()
3036 strtab = dmam_alloc_coherent(smmu->dev, size, &cfg->strtab_dma, in arm_smmu_init_strtab_linear()
3039 dev_err(smmu->dev, in arm_smmu_init_strtab_linear()
3045 cfg->num_l1_ents = 1 << smmu->sid_bits; in arm_smmu_init_strtab_linear()
3049 reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits); in arm_smmu_init_strtab_linear()
3056 static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) in arm_smmu_init_strtab() argument
3061 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_init_strtab()
3062 ret = arm_smmu_init_strtab_2lvl(smmu); in arm_smmu_init_strtab()
3064 ret = arm_smmu_init_strtab_linear(smmu); in arm_smmu_init_strtab()
3070 reg = smmu->strtab_cfg.strtab_dma & STRTAB_BASE_ADDR_MASK; in arm_smmu_init_strtab()
3072 smmu->strtab_cfg.strtab_base = reg; in arm_smmu_init_strtab()
3075 set_bit(0, smmu->vmid_map); in arm_smmu_init_strtab()
3079 static int arm_smmu_init_structures(struct arm_smmu_device *smmu) in arm_smmu_init_structures() argument
3083 mutex_init(&smmu->streams_mutex); in arm_smmu_init_structures()
3084 smmu->streams = RB_ROOT; in arm_smmu_init_structures()
3086 ret = arm_smmu_init_queues(smmu); in arm_smmu_init_structures()
3090 return arm_smmu_init_strtab(smmu); in arm_smmu_init_structures()
3093 static int arm_smmu_write_reg_sync(struct arm_smmu_device *smmu, u32 val, in arm_smmu_write_reg_sync() argument
3098 writel_relaxed(val, smmu->base + reg_off); in arm_smmu_write_reg_sync()
3099 return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val, in arm_smmu_write_reg_sync()
3104 static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr) in arm_smmu_update_gbpa() argument
3107 u32 reg, __iomem *gbpa = smmu->base + ARM_SMMU_GBPA; in arm_smmu_update_gbpa()
3121 dev_err(smmu->dev, "GBPA not responding to update\n"); in arm_smmu_update_gbpa()
3135 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_write_msi_msg() local
3141 writeq_relaxed(doorbell, smmu->base + cfg[0]); in arm_smmu_write_msi_msg()
3142 writel_relaxed(msg->data, smmu->base + cfg[1]); in arm_smmu_write_msi_msg()
3143 writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]); in arm_smmu_write_msi_msg()
3146 static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) in arm_smmu_setup_msis() argument
3149 struct device *dev = smmu->dev; in arm_smmu_setup_msis()
3152 writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); in arm_smmu_setup_msis()
3153 writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); in arm_smmu_setup_msis()
3155 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_msis()
3156 writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0); in arm_smmu_setup_msis()
3160 if (!(smmu->features & ARM_SMMU_FEAT_MSI)) in arm_smmu_setup_msis()
3164 dev_info(smmu->dev, "msi_domain absent - falling back to wired irqs\n"); in arm_smmu_setup_msis()
3175 smmu->evtq.q.irq = msi_get_virq(dev, EVTQ_MSI_INDEX); in arm_smmu_setup_msis()
3176 smmu->gerr_irq = msi_get_virq(dev, GERROR_MSI_INDEX); in arm_smmu_setup_msis()
3177 smmu->priq.q.irq = msi_get_virq(dev, PRIQ_MSI_INDEX); in arm_smmu_setup_msis()
3183 static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) in arm_smmu_setup_unique_irqs() argument
3187 arm_smmu_setup_msis(smmu); in arm_smmu_setup_unique_irqs()
3190 irq = smmu->evtq.q.irq; in arm_smmu_setup_unique_irqs()
3192 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3195 "arm-smmu-v3-evtq", smmu); in arm_smmu_setup_unique_irqs()
3197 dev_warn(smmu->dev, "failed to enable evtq irq\n"); in arm_smmu_setup_unique_irqs()
3199 dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3202 irq = smmu->gerr_irq; in arm_smmu_setup_unique_irqs()
3204 ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler, in arm_smmu_setup_unique_irqs()
3205 0, "arm-smmu-v3-gerror", smmu); in arm_smmu_setup_unique_irqs()
3207 dev_warn(smmu->dev, "failed to enable gerror irq\n"); in arm_smmu_setup_unique_irqs()
3209 dev_warn(smmu->dev, "no gerr irq - errors will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3212 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_setup_unique_irqs()
3213 irq = smmu->priq.q.irq; in arm_smmu_setup_unique_irqs()
3215 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3219 smmu); in arm_smmu_setup_unique_irqs()
3221 dev_warn(smmu->dev, in arm_smmu_setup_unique_irqs()
3224 dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); in arm_smmu_setup_unique_irqs()
3229 static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) in arm_smmu_setup_irqs() argument
3235 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL, in arm_smmu_setup_irqs()
3238 dev_err(smmu->dev, "failed to disable irqs\n"); in arm_smmu_setup_irqs()
3242 irq = smmu->combined_irq; in arm_smmu_setup_irqs()
3248 ret = devm_request_threaded_irq(smmu->dev, irq, in arm_smmu_setup_irqs()
3252 "arm-smmu-v3-combined-irq", smmu); in arm_smmu_setup_irqs()
3254 dev_warn(smmu->dev, "failed to enable combined irq\n"); in arm_smmu_setup_irqs()
3256 arm_smmu_setup_unique_irqs(smmu); in arm_smmu_setup_irqs()
3258 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_irqs()
3262 ret = arm_smmu_write_reg_sync(smmu, irqen_flags, in arm_smmu_setup_irqs()
3265 dev_warn(smmu->dev, "failed to enable irqs\n"); in arm_smmu_setup_irqs()
3270 static int arm_smmu_device_disable(struct arm_smmu_device *smmu) in arm_smmu_device_disable() argument
3274 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_CR0, ARM_SMMU_CR0ACK); in arm_smmu_device_disable()
3276 dev_err(smmu->dev, "failed to clear cr0\n"); in arm_smmu_device_disable()
3281 static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass) in arm_smmu_device_reset() argument
3288 reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); in arm_smmu_device_reset()
3290 dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); in arm_smmu_device_reset()
3292 arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0); in arm_smmu_device_reset()
3295 ret = arm_smmu_device_disable(smmu); in arm_smmu_device_reset()
3306 writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); in arm_smmu_device_reset()
3311 if (smmu->features & ARM_SMMU_FEAT_E2H) in arm_smmu_device_reset()
3314 writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); in arm_smmu_device_reset()
3317 writeq_relaxed(smmu->strtab_cfg.strtab_base, in arm_smmu_device_reset()
3318 smmu->base + ARM_SMMU_STRTAB_BASE); in arm_smmu_device_reset()
3319 writel_relaxed(smmu->strtab_cfg.strtab_base_cfg, in arm_smmu_device_reset()
3320 smmu->base + ARM_SMMU_STRTAB_BASE_CFG); in arm_smmu_device_reset()
3323 writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); in arm_smmu_device_reset()
3324 writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); in arm_smmu_device_reset()
3325 writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); in arm_smmu_device_reset()
3328 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3331 dev_err(smmu->dev, "failed to enable command queue\n"); in arm_smmu_device_reset()
3337 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3340 if (smmu->features & ARM_SMMU_FEAT_HYP) { in arm_smmu_device_reset()
3342 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3346 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3349 writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); in arm_smmu_device_reset()
3350 writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); in arm_smmu_device_reset()
3351 writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); in arm_smmu_device_reset()
3354 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3357 dev_err(smmu->dev, "failed to enable event queue\n"); in arm_smmu_device_reset()
3362 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_device_reset()
3363 writeq_relaxed(smmu->priq.q.q_base, in arm_smmu_device_reset()
3364 smmu->base + ARM_SMMU_PRIQ_BASE); in arm_smmu_device_reset()
3365 writel_relaxed(smmu->priq.q.llq.prod, in arm_smmu_device_reset()
3366 smmu->page1 + ARM_SMMU_PRIQ_PROD); in arm_smmu_device_reset()
3367 writel_relaxed(smmu->priq.q.llq.cons, in arm_smmu_device_reset()
3368 smmu->page1 + ARM_SMMU_PRIQ_CONS); in arm_smmu_device_reset()
3371 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3374 dev_err(smmu->dev, "failed to enable PRI queue\n"); in arm_smmu_device_reset()
3379 if (smmu->features & ARM_SMMU_FEAT_ATS) { in arm_smmu_device_reset()
3381 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3384 dev_err(smmu->dev, "failed to enable ATS check\n"); in arm_smmu_device_reset()
3389 ret = arm_smmu_setup_irqs(smmu); in arm_smmu_device_reset()
3391 dev_err(smmu->dev, "failed to setup irqs\n"); in arm_smmu_device_reset()
3402 ret = arm_smmu_update_gbpa(smmu, 0, GBPA_ABORT); in arm_smmu_device_reset()
3406 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3409 dev_err(smmu->dev, "failed to enable SMMU interface\n"); in arm_smmu_device_reset()
3416 static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) in arm_smmu_device_hw_probe() argument
3419 bool coherent = smmu->features & ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_hw_probe()
3422 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); in arm_smmu_device_hw_probe()
3426 smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
3429 smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB; in arm_smmu_device_hw_probe()
3438 smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
3442 smmu->features |= ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
3446 smmu->features |= ARM_SMMU_FEAT_TT_LE; in arm_smmu_device_hw_probe()
3450 dev_err(smmu->dev, "unknown/unsupported TT endianness!\n"); in arm_smmu_device_hw_probe()
3456 smmu->features |= ARM_SMMU_FEAT_PRI; in arm_smmu_device_hw_probe()
3459 smmu->features |= ARM_SMMU_FEAT_ATS; in arm_smmu_device_hw_probe()
3462 smmu->features |= ARM_SMMU_FEAT_SEV; in arm_smmu_device_hw_probe()
3465 smmu->features |= ARM_SMMU_FEAT_MSI; in arm_smmu_device_hw_probe()
3467 smmu->options |= ARM_SMMU_OPT_MSIPOLL; in arm_smmu_device_hw_probe()
3471 smmu->features |= ARM_SMMU_FEAT_HYP; in arm_smmu_device_hw_probe()
3473 smmu->features |= ARM_SMMU_FEAT_E2H; in arm_smmu_device_hw_probe()
3481 dev_warn(smmu->dev, "IDR0.COHACC overridden by FW configuration (%s)\n", in arm_smmu_device_hw_probe()
3486 smmu->features |= ARM_SMMU_FEAT_STALL_FORCE; in arm_smmu_device_hw_probe()
3489 smmu->features |= ARM_SMMU_FEAT_STALLS; in arm_smmu_device_hw_probe()
3493 smmu->features |= ARM_SMMU_FEAT_TRANS_S1; in arm_smmu_device_hw_probe()
3496 smmu->features |= ARM_SMMU_FEAT_TRANS_S2; in arm_smmu_device_hw_probe()
3499 dev_err(smmu->dev, "no translation support!\n"); in arm_smmu_device_hw_probe()
3506 smmu->ias = 40; in arm_smmu_device_hw_probe()
3511 dev_err(smmu->dev, "AArch64 table format not supported!\n"); in arm_smmu_device_hw_probe()
3516 smmu->asid_bits = reg & IDR0_ASID16 ? 16 : 8; in arm_smmu_device_hw_probe()
3517 smmu->vmid_bits = reg & IDR0_VMID16 ? 16 : 8; in arm_smmu_device_hw_probe()
3520 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1); in arm_smmu_device_hw_probe()
3522 dev_err(smmu->dev, "embedded implementation not supported\n"); in arm_smmu_device_hw_probe()
3527 smmu->cmdq.q.llq.max_n_shift = min_t(u32, CMDQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
3529 if (smmu->cmdq.q.llq.max_n_shift <= ilog2(CMDQ_BATCH_ENTRIES)) { in arm_smmu_device_hw_probe()
3536 dev_err(smmu->dev, "command queue size <= %d entries not supported\n", in arm_smmu_device_hw_probe()
3541 smmu->evtq.q.llq.max_n_shift = min_t(u32, EVTQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
3543 smmu->priq.q.llq.max_n_shift = min_t(u32, PRIQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
3547 smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg); in arm_smmu_device_hw_probe()
3548 smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg); in arm_smmu_device_hw_probe()
3549 smmu->iommu.max_pasids = 1UL << smmu->ssid_bits; in arm_smmu_device_hw_probe()
3555 if (smmu->sid_bits <= STRTAB_SPLIT) in arm_smmu_device_hw_probe()
3556 smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
3559 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3); in arm_smmu_device_hw_probe()
3561 smmu->features |= ARM_SMMU_FEAT_RANGE_INV; in arm_smmu_device_hw_probe()
3564 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); in arm_smmu_device_hw_probe()
3567 smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg); in arm_smmu_device_hw_probe()
3571 smmu->pgsize_bitmap |= SZ_64K | SZ_512M; in arm_smmu_device_hw_probe()
3573 smmu->pgsize_bitmap |= SZ_16K | SZ_32M; in arm_smmu_device_hw_probe()
3575 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; in arm_smmu_device_hw_probe()
3579 smmu->features |= ARM_SMMU_FEAT_VAX; in arm_smmu_device_hw_probe()
3584 smmu->oas = 32; in arm_smmu_device_hw_probe()
3587 smmu->oas = 36; in arm_smmu_device_hw_probe()
3590 smmu->oas = 40; in arm_smmu_device_hw_probe()
3593 smmu->oas = 42; in arm_smmu_device_hw_probe()
3596 smmu->oas = 44; in arm_smmu_device_hw_probe()
3599 smmu->oas = 52; in arm_smmu_device_hw_probe()
3600 smmu->pgsize_bitmap |= 1ULL << 42; /* 4TB */ in arm_smmu_device_hw_probe()
3603 dev_info(smmu->dev, in arm_smmu_device_hw_probe()
3607 smmu->oas = 48; in arm_smmu_device_hw_probe()
3611 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
3613 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
3616 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas))) in arm_smmu_device_hw_probe()
3617 dev_warn(smmu->dev, in arm_smmu_device_hw_probe()
3620 smmu->ias = max(smmu->ias, smmu->oas); in arm_smmu_device_hw_probe()
3622 if (arm_smmu_sva_supported(smmu)) in arm_smmu_device_hw_probe()
3623 smmu->features |= ARM_SMMU_FEAT_SVA; in arm_smmu_device_hw_probe()
3625 dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n", in arm_smmu_device_hw_probe()
3626 smmu->ias, smmu->oas, smmu->features); in arm_smmu_device_hw_probe()
3631 static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu) in acpi_smmu_get_options() argument
3635 smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY; in acpi_smmu_get_options()
3638 smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; in acpi_smmu_get_options()
3642 dev_notice(smmu->dev, "option mask 0x%x\n", smmu->options); in acpi_smmu_get_options()
3646 struct arm_smmu_device *smmu) in arm_smmu_device_acpi_probe() argument
3649 struct device *dev = smmu->dev; in arm_smmu_device_acpi_probe()
3657 acpi_smmu_get_options(iort_smmu->model, smmu); in arm_smmu_device_acpi_probe()
3660 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_acpi_probe()
3666 struct arm_smmu_device *smmu) in arm_smmu_device_acpi_probe() argument
3673 struct arm_smmu_device *smmu) in arm_smmu_device_dt_probe() argument
3686 parse_driver_options(smmu); in arm_smmu_device_dt_probe()
3689 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_dt_probe()
3694 static unsigned long arm_smmu_resource_size(struct arm_smmu_device *smmu) in arm_smmu_resource_size() argument
3696 if (smmu->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY) in arm_smmu_resource_size()
3710 static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu) in arm_smmu_rmr_install_bypass_ste() argument
3716 iort_get_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_ste()
3725 ret = arm_smmu_init_sid_strtab(smmu, rmr->sids[i]); in arm_smmu_rmr_install_bypass_ste()
3727 dev_err(smmu->dev, "RMR SID(0x%x) bypass failed\n", in arm_smmu_rmr_install_bypass_ste()
3732 step = arm_smmu_get_step_for_sid(smmu, rmr->sids[i]); in arm_smmu_rmr_install_bypass_ste()
3737 iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_ste()
3745 struct arm_smmu_device *smmu; in arm_smmu_device_probe() local
3749 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); in arm_smmu_device_probe()
3750 if (!smmu) in arm_smmu_device_probe()
3752 smmu->dev = dev; in arm_smmu_device_probe()
3755 ret = arm_smmu_device_dt_probe(pdev, smmu); in arm_smmu_device_probe()
3757 ret = arm_smmu_device_acpi_probe(pdev, smmu); in arm_smmu_device_probe()
3769 if (resource_size(res) < arm_smmu_resource_size(smmu)) { in arm_smmu_device_probe()
3779 smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ); in arm_smmu_device_probe()
3780 if (IS_ERR(smmu->base)) in arm_smmu_device_probe()
3781 return PTR_ERR(smmu->base); in arm_smmu_device_probe()
3783 if (arm_smmu_resource_size(smmu) > SZ_64K) { in arm_smmu_device_probe()
3784 smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K, in arm_smmu_device_probe()
3786 if (IS_ERR(smmu->page1)) in arm_smmu_device_probe()
3787 return PTR_ERR(smmu->page1); in arm_smmu_device_probe()
3789 smmu->page1 = smmu->base; in arm_smmu_device_probe()
3796 smmu->combined_irq = irq; in arm_smmu_device_probe()
3800 smmu->evtq.q.irq = irq; in arm_smmu_device_probe()
3804 smmu->priq.q.irq = irq; in arm_smmu_device_probe()
3808 smmu->gerr_irq = irq; in arm_smmu_device_probe()
3811 ret = arm_smmu_device_hw_probe(smmu); in arm_smmu_device_probe()
3816 ret = arm_smmu_init_structures(smmu); in arm_smmu_device_probe()
3821 platform_set_drvdata(pdev, smmu); in arm_smmu_device_probe()
3824 arm_smmu_rmr_install_bypass_ste(smmu); in arm_smmu_device_probe()
3827 ret = arm_smmu_device_reset(smmu, bypass); in arm_smmu_device_probe()
3832 ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, in arm_smmu_device_probe()
3837 ret = iommu_device_register(&smmu->iommu, &arm_smmu_ops, dev); in arm_smmu_device_probe()
3840 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_probe()
3849 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_remove() local
3851 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_remove()
3852 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_remove()
3853 arm_smmu_device_disable(smmu); in arm_smmu_device_remove()
3854 iopf_queue_free(smmu->evtq.iopf); in arm_smmu_device_remove()
3861 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_shutdown() local
3863 arm_smmu_device_disable(smmu); in arm_smmu_device_shutdown()