Lines Matching refs:smmu
28 static u32 arm_smmu_read_ns(struct arm_smmu_device *smmu, int page, in arm_smmu_read_ns() argument
33 return readl_relaxed(arm_smmu_page(smmu, page) + offset); in arm_smmu_read_ns()
36 static void arm_smmu_write_ns(struct arm_smmu_device *smmu, int page, in arm_smmu_write_ns() argument
41 writel_relaxed(val, arm_smmu_page(smmu, page) + offset); in arm_smmu_write_ns()
52 struct arm_smmu_device smmu; member
56 static int cavium_cfg_probe(struct arm_smmu_device *smmu) in cavium_cfg_probe() argument
59 struct cavium_smmu *cs = container_of(smmu, struct cavium_smmu, smmu); in cavium_cfg_probe()
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()
66 dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n"); in cavium_cfg_probe()
74 struct cavium_smmu *cs = container_of(smmu_domain->smmu, in cavium_init_context()
75 struct cavium_smmu, smmu); in cavium_init_context()
90 static struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smmu) in cavium_smmu_impl_init() argument
94 cs = devm_krealloc(smmu->dev, smmu, sizeof(*cs), GFP_KERNEL); in cavium_smmu_impl_init()
98 cs->smmu.impl = &cavium_impl; in cavium_smmu_impl_init()
100 return &cs->smmu; in cavium_smmu_impl_init()
110 int arm_mmu500_reset(struct arm_smmu_device *smmu) in arm_mmu500_reset() argument
119 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID7); in arm_mmu500_reset()
121 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sACR); in arm_mmu500_reset()
129 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sACR, reg); in arm_mmu500_reset()
135 for (i = 0; i < smmu->num_context_banks; ++i) { in arm_mmu500_reset()
136 reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR); in arm_mmu500_reset()
138 arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg); in arm_mmu500_reset()
139 reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR); in arm_mmu500_reset()
141 …dev_warn_once(smmu->dev, "Failed to disable prefetcher [errata #841119 and #826419], check ACR.CAC… in arm_mmu500_reset()
151 static u64 mrvl_mmu500_readq(struct arm_smmu_device *smmu, int page, int off) in mrvl_mmu500_readq() argument
157 return hi_lo_readq_relaxed(arm_smmu_page(smmu, page) + off); in mrvl_mmu500_readq()
160 static void mrvl_mmu500_writeq(struct arm_smmu_device *smmu, int page, int off, in mrvl_mmu500_writeq() argument
167 hi_lo_writeq_relaxed(val, arm_smmu_page(smmu, page) + off); in mrvl_mmu500_writeq()
170 static int mrvl_mmu500_cfg_probe(struct arm_smmu_device *smmu) in mrvl_mmu500_cfg_probe() argument
179 smmu->features &= ~(ARM_SMMU_FEAT_FMT_AARCH64_4K | in mrvl_mmu500_cfg_probe()
194 struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) in arm_smmu_impl_init() argument
196 const struct device_node *np = smmu->dev->of_node; in arm_smmu_impl_init()
203 switch (smmu->model) { in arm_smmu_impl_init()
205 smmu->impl = &arm_mmu500_impl; in arm_smmu_impl_init()
208 return cavium_smmu_impl_init(smmu); in arm_smmu_impl_init()
215 smmu->impl = &calxeda_impl; in arm_smmu_impl_init()
220 return nvidia_smmu_impl_init(smmu); in arm_smmu_impl_init()
223 smmu = qcom_smmu_impl_init(smmu); in arm_smmu_impl_init()
226 smmu->impl = &mrvl_mmu500_impl; in arm_smmu_impl_init()
228 return smmu; in arm_smmu_impl_init()