Lines Matching refs:smmu
17 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) in to_qcom_smmu() argument
19 return container_of(smmu, struct qcom_smmu, smmu); in to_qcom_smmu()
22 static void qcom_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, in qcom_smmu_tlb_sync() argument
28 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL); in qcom_smmu_tlb_sync()
31 reg = arm_smmu_readl(smmu, page, status); in qcom_smmu_tlb_sync()
39 qcom_smmu_tlb_sync_debug(smmu); in qcom_smmu_tlb_sync()
42 static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx, in qcom_adreno_smmu_write_sctlr() argument
45 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); in qcom_adreno_smmu_write_sctlr()
56 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in qcom_adreno_smmu_write_sctlr()
64 struct arm_smmu_device *smmu = smmu_domain->smmu; in qcom_adreno_smmu_get_fault_info() local
66 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); in qcom_adreno_smmu_get_fault_info()
67 info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0); in qcom_adreno_smmu_get_fault_info()
68 info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1); in qcom_adreno_smmu_get_fault_info()
69 info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR); in qcom_adreno_smmu_get_fault_info()
70 info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx)); in qcom_adreno_smmu_get_fault_info()
71 info->ttbr0 = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); in qcom_adreno_smmu_get_fault_info()
72 info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR); in qcom_adreno_smmu_get_fault_info()
79 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu_domain->smmu); in qcom_adreno_smmu_set_stall()
91 struct arm_smmu_device *smmu = smmu_domain->smmu; in qcom_adreno_smmu_resume_translation() local
97 arm_smmu_cb_write(smmu, cfg->cbndx, ARM_SMMU_CB_RESUME, reg); in qcom_adreno_smmu_resume_translation()
142 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; in qcom_adreno_smmu_set_ttbr0_cfg()
172 arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); in qcom_adreno_smmu_set_ttbr0_cfg()
178 struct arm_smmu_device *smmu, in qcom_adreno_smmu_alloc_context_bank() argument
192 count = smmu->num_context_banks; in qcom_adreno_smmu_alloc_context_bank()
195 return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); in qcom_adreno_smmu_alloc_context_bank()
198 static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) in qcom_adreno_can_do_ttbr1() argument
200 const struct device_node *np = smmu->dev->of_node; in qcom_adreno_can_do_ttbr1()
224 if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) && in qcom_adreno_smmu_init_context()
269 static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) in qcom_smmu_cfg_probe() argument
271 unsigned int last_s2cr = ARM_SMMU_GR0_S2CR(smmu->num_mapping_groups - 1); in qcom_smmu_cfg_probe()
272 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); in qcom_smmu_cfg_probe()
286 arm_smmu_gr0_write(smmu, last_s2cr, reg); in qcom_smmu_cfg_probe()
287 reg = arm_smmu_gr0_read(smmu, last_s2cr); in qcom_smmu_cfg_probe()
290 qsmmu->bypass_cbndx = smmu->num_context_banks - 1; in qcom_smmu_cfg_probe()
292 set_bit(qsmmu->bypass_cbndx, smmu->context_map); in qcom_smmu_cfg_probe()
294 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); in qcom_smmu_cfg_probe()
297 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg); in qcom_smmu_cfg_probe()
300 for (i = 0; i < smmu->num_mapping_groups; i++) { in qcom_smmu_cfg_probe()
301 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); in qcom_smmu_cfg_probe()
306 smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr); in qcom_smmu_cfg_probe()
307 smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); in qcom_smmu_cfg_probe()
308 smmu->smrs[i].valid = true; in qcom_smmu_cfg_probe()
310 smmu->s2crs[i].type = S2CR_TYPE_BYPASS; in qcom_smmu_cfg_probe()
311 smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT; in qcom_smmu_cfg_probe()
312 smmu->s2crs[i].cbndx = 0xff; in qcom_smmu_cfg_probe()
319 static void qcom_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) in qcom_smmu_write_s2cr() argument
321 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; in qcom_smmu_write_s2cr()
322 struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); in qcom_smmu_write_s2cr()
351 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); in qcom_smmu_write_s2cr()
362 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) in qcom_sdm845_smmu500_reset() argument
366 arm_mmu500_reset(smmu); in qcom_sdm845_smmu500_reset()
376 dev_warn(smmu->dev, "Failed to turn off SAFE logic\n"); in qcom_sdm845_smmu500_reset()
424 static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, in qcom_smmu_create() argument
427 const struct device_node *np = smmu->dev->of_node; in qcom_smmu_create()
440 return smmu; in qcom_smmu_create()
446 qsmmu = devm_krealloc(smmu->dev, smmu, sizeof(*qsmmu), GFP_KERNEL); in qcom_smmu_create()
450 qsmmu->smmu.impl = impl; in qcom_smmu_create()
453 return &qsmmu->smmu; in qcom_smmu_create()
533 struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) in qcom_smmu_impl_init() argument
535 const struct device_node *np = smmu->dev->of_node; in qcom_smmu_impl_init()
542 return qcom_smmu_create(smmu, &qcom_smmu_500_impl0_data); in qcom_smmu_impl_init()
548 return qcom_smmu_create(smmu, match->data); in qcom_smmu_impl_init()
550 return smmu; in qcom_smmu_impl_init()