Lines Matching refs:arm_smmu_cb_write
246 arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx, in arm_smmu_tlb_inv_context_s1()
277 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
305 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
418 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); in arm_smmu_context_fault()
521 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, 0); in arm_smmu_write_context_bank()
566 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR2, cb->tcr[1]); in arm_smmu_write_context_bank()
567 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR, cb->tcr[0]); in arm_smmu_write_context_bank()
571 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_CONTEXTIDR, cfg->asid); in arm_smmu_write_context_bank()
572 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
573 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
583 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_S1_MAIR0, cb->mair[0]); in arm_smmu_write_context_bank()
584 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_S1_MAIR1, cb->mair[1]); in arm_smmu_write_context_bank()
598 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in arm_smmu_write_context_bank()
1269 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ATS1PR, va); in arm_smmu_iova_to_phys_hard()
1607 arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); in arm_smmu_device_reset()