Lines Matching refs:iommu
33 struct intel_iommu *iommu; member
40 struct intel_iommu *iommu; member
47 struct intel_iommu *iommu; member
83 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
87 static bool ir_pre_enabled(struct intel_iommu *iommu) in ir_pre_enabled() argument
89 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED); in ir_pre_enabled()
92 static void clear_ir_pre_enabled(struct intel_iommu *iommu) in clear_ir_pre_enabled() argument
94 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED; in clear_ir_pre_enabled()
97 static void init_ir_status(struct intel_iommu *iommu) in init_ir_status() argument
101 gsts = readl(iommu->reg + DMAR_GSTS_REG); in init_ir_status()
103 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED; in init_ir_status()
106 static int alloc_irte(struct intel_iommu *iommu, in alloc_irte() argument
109 struct ir_table *table = iommu->ir_table; in alloc_irte()
122 if (mask > ecap_max_handle_mask(iommu->ecap)) { in alloc_irte()
125 ecap_max_handle_mask(iommu->ecap)); in alloc_irte()
133 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id); in alloc_irte()
135 irq_iommu->iommu = iommu; in alloc_irte()
146 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) in qi_flush_iec() argument
156 return qi_submit_sync(iommu, &desc, 1, 0); in qi_flush_iec()
162 struct intel_iommu *iommu; in modify_irte() local
172 iommu = irq_iommu->iommu; in modify_irte()
175 irte = &iommu->ir_table->base[index]; in modify_irte()
194 __iommu_flush_cache(iommu, irte, sizeof(*irte)); in modify_irte()
196 rc = qi_flush_iec(iommu, index, 0); in modify_irte()
210 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu) in map_hpet_to_iommu()
211 return ir_hpet[i].iommu; in map_hpet_to_iommu()
221 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu) in map_ioapic_to_iommu()
222 return ir_ioapic[i].iommu; in map_ioapic_to_iommu()
231 return drhd ? drhd->iommu->ir_domain : NULL; in map_dev_to_ir()
237 struct intel_iommu *iommu; in clear_entries() local
243 iommu = irq_iommu->iommu; in clear_entries()
246 start = iommu->ir_table->base + index; in clear_entries()
253 bitmap_release_region(iommu->ir_table->bitmap, index, in clear_entries()
256 return qi_flush_iec(iommu, index, irq_iommu->irte_mask); in clear_entries()
316 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) { in set_ioapic_sid()
343 if (ir_hpet[i].iommu && ir_hpet[i].id == id) { in set_hpet_sid()
429 static int iommu_load_old_irte(struct intel_iommu *iommu) in iommu_load_old_irte() argument
438 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG); in iommu_load_old_irte()
452 memcpy(iommu->ir_table->base, old_ir_table, size); in iommu_load_old_irte()
454 __iommu_flush_cache(iommu, iommu->ir_table->base, size); in iommu_load_old_irte()
461 if (iommu->ir_table->base[i].present) in iommu_load_old_irte()
462 bitmap_set(iommu->ir_table->bitmap, i, 1); in iommu_load_old_irte()
471 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode) in iommu_set_irq_remapping() argument
477 addr = virt_to_phys((void *)iommu->ir_table->base); in iommu_set_irq_remapping()
479 raw_spin_lock_irqsave(&iommu->register_lock, flags); in iommu_set_irq_remapping()
481 dmar_writeq(iommu->reg + DMAR_IRTA_REG, in iommu_set_irq_remapping()
485 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG); in iommu_set_irq_remapping()
487 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_set_irq_remapping()
489 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in iommu_set_irq_remapping()
495 if (!cap_esirtps(iommu->cap)) in iommu_set_irq_remapping()
496 qi_global_iec(iommu); in iommu_set_irq_remapping()
499 static void iommu_enable_irq_remapping(struct intel_iommu *iommu) in iommu_enable_irq_remapping() argument
504 raw_spin_lock_irqsave(&iommu->register_lock, flags); in iommu_enable_irq_remapping()
507 iommu->gcmd |= DMA_GCMD_IRE; in iommu_enable_irq_remapping()
508 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in iommu_enable_irq_remapping()
509 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_enable_irq_remapping()
514 iommu->gcmd &= ~DMA_GCMD_CFI; in iommu_enable_irq_remapping()
515 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in iommu_enable_irq_remapping()
516 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_enable_irq_remapping()
530 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in iommu_enable_irq_remapping()
533 static int intel_setup_irq_remapping(struct intel_iommu *iommu) in intel_setup_irq_remapping() argument
540 if (iommu->ir_table) in intel_setup_irq_remapping()
547 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO, in intel_setup_irq_remapping()
551 iommu->seq_id, INTR_REMAP_PAGE_ORDER); in intel_setup_irq_remapping()
557 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id); in intel_setup_irq_remapping()
561 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id); in intel_setup_irq_remapping()
565 iommu->ir_domain = in intel_setup_irq_remapping()
569 iommu); in intel_setup_irq_remapping()
570 if (!iommu->ir_domain) { in intel_setup_irq_remapping()
571 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id); in intel_setup_irq_remapping()
575 irq_domain_update_bus_token(iommu->ir_domain, DOMAIN_BUS_DMAR); in intel_setup_irq_remapping()
576 iommu->ir_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT | in intel_setup_irq_remapping()
579 if (cap_caching_mode(iommu->cap)) in intel_setup_irq_remapping()
580 iommu->ir_domain->msi_parent_ops = &virt_dmar_msi_parent_ops; in intel_setup_irq_remapping()
582 iommu->ir_domain->msi_parent_ops = &dmar_msi_parent_ops; in intel_setup_irq_remapping()
586 iommu->ir_table = ir_table; in intel_setup_irq_remapping()
592 if (!iommu->qi) { in intel_setup_irq_remapping()
596 dmar_fault(-1, iommu); in intel_setup_irq_remapping()
597 dmar_disable_qi(iommu); in intel_setup_irq_remapping()
599 if (dmar_enable_qi(iommu)) { in intel_setup_irq_remapping()
605 init_ir_status(iommu); in intel_setup_irq_remapping()
607 if (ir_pre_enabled(iommu)) { in intel_setup_irq_remapping()
610 iommu->name); in intel_setup_irq_remapping()
611 clear_ir_pre_enabled(iommu); in intel_setup_irq_remapping()
612 iommu_disable_irq_remapping(iommu); in intel_setup_irq_remapping()
613 } else if (iommu_load_old_irte(iommu)) in intel_setup_irq_remapping()
615 iommu->name); in intel_setup_irq_remapping()
618 iommu->name); in intel_setup_irq_remapping()
621 iommu_set_irq_remapping(iommu, eim_mode); in intel_setup_irq_remapping()
626 irq_domain_remove(iommu->ir_domain); in intel_setup_irq_remapping()
627 iommu->ir_domain = NULL; in intel_setup_irq_remapping()
637 iommu->ir_table = NULL; in intel_setup_irq_remapping()
642 static void intel_teardown_irq_remapping(struct intel_iommu *iommu) in intel_teardown_irq_remapping() argument
646 if (iommu && iommu->ir_table) { in intel_teardown_irq_remapping()
647 if (iommu->ir_domain) { in intel_teardown_irq_remapping()
648 fn = iommu->ir_domain->fwnode; in intel_teardown_irq_remapping()
650 irq_domain_remove(iommu->ir_domain); in intel_teardown_irq_remapping()
652 iommu->ir_domain = NULL; in intel_teardown_irq_remapping()
654 free_pages((unsigned long)iommu->ir_table->base, in intel_teardown_irq_remapping()
656 bitmap_free(iommu->ir_table->bitmap); in intel_teardown_irq_remapping()
657 kfree(iommu->ir_table); in intel_teardown_irq_remapping()
658 iommu->ir_table = NULL; in intel_teardown_irq_remapping()
665 static void iommu_disable_irq_remapping(struct intel_iommu *iommu) in iommu_disable_irq_remapping() argument
670 if (!ecap_ir_support(iommu->ecap)) in iommu_disable_irq_remapping()
677 if (!cap_esirtps(iommu->cap)) in iommu_disable_irq_remapping()
678 qi_global_iec(iommu); in iommu_disable_irq_remapping()
680 raw_spin_lock_irqsave(&iommu->register_lock, flags); in iommu_disable_irq_remapping()
682 sts = readl(iommu->reg + DMAR_GSTS_REG); in iommu_disable_irq_remapping()
686 iommu->gcmd &= ~DMA_GCMD_IRE; in iommu_disable_irq_remapping()
687 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in iommu_disable_irq_remapping()
689 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, in iommu_disable_irq_remapping()
693 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in iommu_disable_irq_remapping()
708 struct intel_iommu *iommu; in intel_cleanup_irq_remapping() local
710 for_each_iommu(iommu, drhd) { in intel_cleanup_irq_remapping()
711 if (ecap_ir_support(iommu->ecap)) { in intel_cleanup_irq_remapping()
712 iommu_disable_irq_remapping(iommu); in intel_cleanup_irq_remapping()
713 intel_teardown_irq_remapping(iommu); in intel_cleanup_irq_remapping()
724 struct intel_iommu *iommu; in intel_prepare_irq_remapping() local
752 for_each_iommu(iommu, drhd) in intel_prepare_irq_remapping()
753 if (!ecap_ir_support(iommu->ecap)) in intel_prepare_irq_remapping()
765 for_each_iommu(iommu, drhd) { in intel_prepare_irq_remapping()
766 if (eim && !ecap_eim_support(iommu->ecap)) { in intel_prepare_irq_remapping()
767 pr_info("%s does not support EIM\n", iommu->name); in intel_prepare_irq_remapping()
777 for_each_iommu(iommu, drhd) { in intel_prepare_irq_remapping()
778 if (intel_setup_irq_remapping(iommu)) { in intel_prepare_irq_remapping()
780 iommu->name); in intel_prepare_irq_remapping()
798 struct intel_iommu *iommu; in set_irq_posting_cap() local
812 for_each_iommu(iommu, drhd) in set_irq_posting_cap()
813 if (!cap_pi_support(iommu->cap)) { in set_irq_posting_cap()
824 struct intel_iommu *iommu; in intel_enable_irq_remapping() local
830 for_each_iommu(iommu, drhd) { in intel_enable_irq_remapping()
831 if (!ir_pre_enabled(iommu)) in intel_enable_irq_remapping()
832 iommu_enable_irq_remapping(iommu); in intel_enable_irq_remapping()
853 struct intel_iommu *iommu, in ir_parse_one_hpet_scope() argument
876 if (ir_hpet[count].iommu == iommu && in ir_parse_one_hpet_scope()
879 else if (ir_hpet[count].iommu == NULL && free == -1) in ir_parse_one_hpet_scope()
887 ir_hpet[free].iommu = iommu; in ir_parse_one_hpet_scope()
898 struct intel_iommu *iommu, in ir_parse_one_ioapic_scope() argument
921 if (ir_ioapic[count].iommu == iommu && in ir_parse_one_ioapic_scope()
924 else if (ir_ioapic[count].iommu == NULL && free == -1) in ir_parse_one_ioapic_scope()
934 ir_ioapic[free].iommu = iommu; in ir_parse_one_ioapic_scope()
937 scope->enumeration_id, drhd->address, iommu->seq_id); in ir_parse_one_ioapic_scope()
943 struct intel_iommu *iommu) in ir_parse_ioapic_hpet_scope() argument
957 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd); in ir_parse_ioapic_hpet_scope()
959 ret = ir_parse_one_hpet_scope(scope, iommu, drhd); in ir_parse_ioapic_hpet_scope()
966 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu) in ir_remove_ioapic_hpet_scope() argument
971 if (ir_hpet[i].iommu == iommu) in ir_remove_ioapic_hpet_scope()
972 ir_hpet[i].iommu = NULL; in ir_remove_ioapic_hpet_scope()
975 if (ir_ioapic[i].iommu == iommu) in ir_remove_ioapic_hpet_scope()
976 ir_ioapic[i].iommu = NULL; in ir_remove_ioapic_hpet_scope()
986 struct intel_iommu *iommu; in parse_ioapics_under_ir() local
990 for_each_iommu(iommu, drhd) { in parse_ioapics_under_ir()
993 if (!ecap_ir_support(iommu->ecap)) in parse_ioapics_under_ir()
996 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu); in parse_ioapics_under_ir()
1037 struct intel_iommu *iommu = NULL; in disable_irq_remapping() local
1042 for_each_iommu(iommu, drhd) { in disable_irq_remapping()
1043 if (!ecap_ir_support(iommu->ecap)) in disable_irq_remapping()
1046 iommu_disable_irq_remapping(iommu); in disable_irq_remapping()
1060 struct intel_iommu *iommu = NULL; in reenable_irq_remapping() local
1062 for_each_iommu(iommu, drhd) in reenable_irq_remapping()
1063 if (iommu->qi) in reenable_irq_remapping()
1064 dmar_reenable_qi(iommu); in reenable_irq_remapping()
1069 for_each_iommu(iommu, drhd) { in reenable_irq_remapping()
1070 if (!ecap_ir_support(iommu->ecap)) in reenable_irq_remapping()
1074 iommu_set_irq_remapping(iommu, eim); in reenable_irq_remapping()
1075 iommu_enable_irq_remapping(iommu); in reenable_irq_remapping()
1321 struct intel_iommu *iommu = domain->host_data; in intel_irq_remapping_alloc() local
1328 if (!info || !iommu) in intel_irq_remapping_alloc()
1343 index = alloc_irte(iommu, &data->irq_2_iommu, nr_irqs); in intel_irq_remapping_alloc()
1415 struct intel_iommu *iommu = NULL; in intel_irq_remapping_select() local
1418 iommu = map_ioapic_to_iommu(fwspec->param[0]); in intel_irq_remapping_select()
1420 iommu = map_hpet_to_iommu(fwspec->param[0]); in intel_irq_remapping_select()
1422 return iommu && d == iommu->ir_domain; in intel_irq_remapping_select()
1451 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu) in dmar_ir_add() argument
1456 ret = intel_cap_audit(CAP_AUDIT_HOTPLUG_IRQR, iommu); in dmar_ir_add()
1460 if (eim && !ecap_eim_support(iommu->ecap)) { in dmar_ir_add()
1462 iommu->reg_phys, iommu->ecap); in dmar_ir_add()
1466 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) { in dmar_ir_add()
1468 iommu->reg_phys); in dmar_ir_add()
1475 ret = intel_setup_irq_remapping(iommu); in dmar_ir_add()
1478 iommu->name); in dmar_ir_add()
1479 intel_teardown_irq_remapping(iommu); in dmar_ir_add()
1480 ir_remove_ioapic_hpet_scope(iommu); in dmar_ir_add()
1482 iommu_enable_irq_remapping(iommu); in dmar_ir_add()
1491 struct intel_iommu *iommu = dmaru->iommu; in dmar_ir_hotplug() local
1495 if (iommu == NULL) in dmar_ir_hotplug()
1497 if (!ecap_ir_support(iommu->ecap)) in dmar_ir_hotplug()
1500 !cap_pi_support(iommu->cap)) in dmar_ir_hotplug()
1504 if (!iommu->ir_table) in dmar_ir_hotplug()
1505 ret = dmar_ir_add(dmaru, iommu); in dmar_ir_hotplug()
1507 if (iommu->ir_table) { in dmar_ir_hotplug()
1508 if (!bitmap_empty(iommu->ir_table->bitmap, in dmar_ir_hotplug()
1512 iommu_disable_irq_remapping(iommu); in dmar_ir_hotplug()
1513 intel_teardown_irq_remapping(iommu); in dmar_ir_hotplug()
1514 ir_remove_ioapic_hpet_scope(iommu); in dmar_ir_hotplug()