Lines Matching refs:gc
54 struct irq_chip_generic *gc; member
69 struct irq_chip_generic *gc = handler->priv->gc; in liointc_chained_handle_irq() local
80 (handler->parent_int_map & gc->mask_cache & in liointc_chained_handle_irq()
90 generic_handle_domain_irq(gc->domain, bit); in liointc_chained_handle_irq()
97 static void liointc_set_bit(struct irq_chip_generic *gc, in liointc_set_bit() argument
102 writel(readl(gc->reg_base + offset) | mask, in liointc_set_bit()
103 gc->reg_base + offset); in liointc_set_bit()
105 writel(readl(gc->reg_base + offset) & ~mask, in liointc_set_bit()
106 gc->reg_base + offset); in liointc_set_bit()
111 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); in liointc_set_type() local
115 irq_gc_lock_irqsave(gc, flags); in liointc_set_type()
118 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); in liointc_set_type()
119 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); in liointc_set_type()
122 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); in liointc_set_type()
123 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); in liointc_set_type()
126 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); in liointc_set_type()
127 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); in liointc_set_type()
130 liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); in liointc_set_type()
131 liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); in liointc_set_type()
134 irq_gc_unlock_irqrestore(gc, flags); in liointc_set_type()
137 irq_gc_unlock_irqrestore(gc, flags); in liointc_set_type()
143 static void liointc_suspend(struct irq_chip_generic *gc) in liointc_suspend() argument
145 struct liointc_priv *priv = gc->private; in liointc_suspend()
147 priv->int_pol = readl(gc->reg_base + LIOINTC_REG_INTC_POL); in liointc_suspend()
148 priv->int_edge = readl(gc->reg_base + LIOINTC_REG_INTC_EDGE); in liointc_suspend()
151 static void liointc_resume(struct irq_chip_generic *gc) in liointc_resume() argument
153 struct liointc_priv *priv = gc->private; in liointc_resume()
157 irq_gc_lock_irqsave(gc, flags); in liointc_resume()
159 writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE); in liointc_resume()
162 writeb(priv->map_cache[i], gc->reg_base + i); in liointc_resume()
163 writel(priv->int_pol, gc->reg_base + LIOINTC_REG_INTC_POL); in liointc_resume()
164 writel(priv->int_edge, gc->reg_base + LIOINTC_REG_INTC_EDGE); in liointc_resume()
166 writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE); in liointc_resume()
167 irq_gc_unlock_irqrestore(gc, flags); in liointc_resume()
203 struct irq_chip_generic *gc; in liointc_init() local
280 gc = irq_get_domain_generic_chip(domain, 0); in liointc_init()
281 gc->private = priv; in liointc_init()
282 gc->reg_base = base; in liointc_init()
283 gc->domain = domain; in liointc_init()
284 gc->suspend = liointc_suspend; in liointc_init()
285 gc->resume = liointc_resume; in liointc_init()
287 ct = gc->chip_types; in liointc_init()
295 gc->mask_cache = 0; in liointc_init()
296 priv->gc = gc; in liointc_init()