Lines Matching refs:gc
76 static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off, in sunxi_sc_nmi_write() argument
79 irq_reg_writel(gc, val, off); in sunxi_sc_nmi_write()
82 static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off) in sunxi_sc_nmi_read() argument
84 return irq_reg_readl(gc, off); in sunxi_sc_nmi_read()
99 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); in sunxi_sc_nmi_set_type() local
100 struct irq_chip_type *ct = gc->chip_types; in sunxi_sc_nmi_set_type()
106 irq_gc_lock(gc); in sunxi_sc_nmi_set_type()
123 irq_gc_unlock(gc); in sunxi_sc_nmi_set_type()
132 for (i = 0; i < gc->num_ct; i++, ct++) in sunxi_sc_nmi_set_type()
136 src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off); in sunxi_sc_nmi_set_type()
139 sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg); in sunxi_sc_nmi_set_type()
141 irq_gc_unlock(gc); in sunxi_sc_nmi_set_type()
150 struct irq_chip_generic *gc; in sunxi_sc_nmi_irq_init() local
177 gc = irq_get_domain_generic_chip(domain, 0); in sunxi_sc_nmi_irq_init()
178 gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node)); in sunxi_sc_nmi_irq_init()
179 if (IS_ERR(gc->reg_base)) { in sunxi_sc_nmi_irq_init()
181 ret = PTR_ERR(gc->reg_base); in sunxi_sc_nmi_irq_init()
185 gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; in sunxi_sc_nmi_irq_init()
186 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in sunxi_sc_nmi_irq_init()
187 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in sunxi_sc_nmi_irq_init()
188 gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit; in sunxi_sc_nmi_irq_init()
189 gc->chip_types[0].chip.irq_set_type = sunxi_sc_nmi_set_type; in sunxi_sc_nmi_irq_init()
190 gc->chip_types[0].chip.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED; in sunxi_sc_nmi_irq_init()
191 gc->chip_types[0].regs.ack = reg_offs->pend; in sunxi_sc_nmi_irq_init()
192 gc->chip_types[0].regs.mask = reg_offs->enable; in sunxi_sc_nmi_irq_init()
193 gc->chip_types[0].regs.type = reg_offs->ctrl; in sunxi_sc_nmi_irq_init()
195 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; in sunxi_sc_nmi_irq_init()
196 gc->chip_types[1].chip.name = gc->chip_types[0].chip.name; in sunxi_sc_nmi_irq_init()
197 gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit; in sunxi_sc_nmi_irq_init()
198 gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit; in sunxi_sc_nmi_irq_init()
199 gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit; in sunxi_sc_nmi_irq_init()
200 gc->chip_types[1].chip.irq_set_type = sunxi_sc_nmi_set_type; in sunxi_sc_nmi_irq_init()
201 gc->chip_types[1].regs.ack = reg_offs->pend; in sunxi_sc_nmi_irq_init()
202 gc->chip_types[1].regs.mask = reg_offs->enable; in sunxi_sc_nmi_irq_init()
203 gc->chip_types[1].regs.type = reg_offs->ctrl; in sunxi_sc_nmi_irq_init()
204 gc->chip_types[1].handler = handle_edge_irq; in sunxi_sc_nmi_irq_init()
207 sunxi_sc_nmi_write(gc, reg_offs->enable, 0); in sunxi_sc_nmi_irq_init()
210 sunxi_sc_nmi_write(gc, reg_offs->pend, SUNXI_NMI_IRQ_BIT); in sunxi_sc_nmi_irq_init()