Lines Matching refs:hc
139 enable_hwirq(struct hfc_pci *hc) in enable_hwirq() argument
141 hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE; in enable_hwirq()
142 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2); in enable_hwirq()
146 disable_hwirq(struct hfc_pci *hc) in disable_hwirq() argument
148 hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE); in disable_hwirq()
149 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2); in disable_hwirq()
156 release_io_hfcpci(struct hfc_pci *hc) in release_io_hfcpci() argument
159 pci_write_config_word(hc->pdev, PCI_COMMAND, 0); in release_io_hfcpci()
160 del_timer(&hc->hw.timer); in release_io_hfcpci()
161 dma_free_coherent(&hc->pdev->dev, 0x8000, hc->hw.fifos, in release_io_hfcpci()
162 hc->hw.dmahandle); in release_io_hfcpci()
163 iounmap(hc->hw.pci_io); in release_io_hfcpci()
170 hfcpci_setmode(struct hfc_pci *hc) in hfcpci_setmode() argument
172 if (hc->hw.protocol == ISDN_P_NT_S0) { in hfcpci_setmode()
173 hc->hw.clkdel = CLKDEL_NT; /* ST-Bit delay for NT-Mode */ in hfcpci_setmode()
174 hc->hw.sctrl |= SCTRL_MODE_NT; /* NT-MODE */ in hfcpci_setmode()
175 hc->hw.states = 1; /* G1 */ in hfcpci_setmode()
177 hc->hw.clkdel = CLKDEL_TE; /* ST-Bit delay for TE-Mode */ in hfcpci_setmode()
178 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */ in hfcpci_setmode()
179 hc->hw.states = 2; /* F2 */ in hfcpci_setmode()
181 Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel); in hfcpci_setmode()
182 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states); in hfcpci_setmode()
184 Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */ in hfcpci_setmode()
185 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl); in hfcpci_setmode()
193 reset_hfcpci(struct hfc_pci *hc) in reset_hfcpci() argument
199 val = Read_hfc(hc, HFCPCI_CHIP_ID); in reset_hfcpci()
202 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO); in reset_hfcpci()
203 disable_hwirq(hc); in reset_hfcpci()
205 pci_write_config_word(hc->pdev, PCI_COMMAND, in reset_hfcpci()
207 val = Read_hfc(hc, HFCPCI_STATUS); in reset_hfcpci()
209 hc->hw.cirm = HFCPCI_RESET; /* Reset On */ in reset_hfcpci()
210 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm); in reset_hfcpci()
213 hc->hw.cirm = 0; /* Reset Off */ in reset_hfcpci()
214 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm); in reset_hfcpci()
215 val = Read_hfc(hc, HFCPCI_STATUS); in reset_hfcpci()
220 val = Read_hfc(hc, HFCPCI_STATUS); in reset_hfcpci()
226 hc->hw.fifo_en = 0x30; /* only D fifos enabled */ in reset_hfcpci()
228 hc->hw.bswapped = 0; /* no exchange */ in reset_hfcpci()
229 hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER; in reset_hfcpci()
230 hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */ in reset_hfcpci()
231 hc->hw.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */ in reset_hfcpci()
232 hc->hw.sctrl_r = 0; in reset_hfcpci()
233 hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE; /* S/T Auto awake */ in reset_hfcpci()
234 hc->hw.mst_m = 0; in reset_hfcpci()
235 if (test_bit(HFC_CFG_MASTER, &hc->cfg)) in reset_hfcpci()
236 hc->hw.mst_m |= HFCPCI_MASTER; /* HFC Master Mode */ in reset_hfcpci()
237 if (test_bit(HFC_CFG_NEG_F0, &hc->cfg)) in reset_hfcpci()
238 hc->hw.mst_m |= HFCPCI_F0_NEGATIV; in reset_hfcpci()
239 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); in reset_hfcpci()
240 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm); in reset_hfcpci()
241 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e); in reset_hfcpci()
242 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt); in reset_hfcpci()
244 hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC | in reset_hfcpci()
246 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); in reset_hfcpci()
249 val = Read_hfc(hc, HFCPCI_INT_S1); in reset_hfcpci()
252 hfcpci_setmode(hc); in reset_hfcpci()
254 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); in reset_hfcpci()
255 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r); in reset_hfcpci()
266 if (test_bit(HFC_CFG_PCM, &hc->cfg)) { in reset_hfcpci()
268 hc->hw.conn = 0x09; in reset_hfcpci()
270 hc->hw.conn = 0x36; /* set data flow directions */ in reset_hfcpci()
271 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) { in reset_hfcpci()
272 Write_hfc(hc, HFCPCI_B1_SSL, 0xC0); in reset_hfcpci()
273 Write_hfc(hc, HFCPCI_B2_SSL, 0xC1); in reset_hfcpci()
274 Write_hfc(hc, HFCPCI_B1_RSL, 0xC0); in reset_hfcpci()
275 Write_hfc(hc, HFCPCI_B2_RSL, 0xC1); in reset_hfcpci()
277 Write_hfc(hc, HFCPCI_B1_SSL, 0x80); in reset_hfcpci()
278 Write_hfc(hc, HFCPCI_B2_SSL, 0x81); in reset_hfcpci()
279 Write_hfc(hc, HFCPCI_B1_RSL, 0x80); in reset_hfcpci()
280 Write_hfc(hc, HFCPCI_B2_RSL, 0x81); in reset_hfcpci()
283 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); in reset_hfcpci()
284 val = Read_hfc(hc, HFCPCI_INT_S2); in reset_hfcpci()
293 struct hfc_pci *hc = from_timer(hc, t, hw.timer); in hfcpci_Timer() local
294 hc->hw.timer.expires = jiffies + 75; in hfcpci_Timer()
307 Sel_BCS(struct hfc_pci *hc, int channel) in Sel_BCS() argument
309 if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) && in Sel_BCS()
310 (hc->bch[0].nr & channel)) in Sel_BCS()
311 return &hc->bch[0]; in Sel_BCS()
312 else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) && in Sel_BCS()
313 (hc->bch[1].nr & channel)) in Sel_BCS()
314 return &hc->bch[1]; in Sel_BCS()
323 hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo) in hfcpci_clear_fifo_rx() argument
329 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2; in hfcpci_clear_fifo_rx()
330 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX; in hfcpci_clear_fifo_rx()
332 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1; in hfcpci_clear_fifo_rx()
333 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX; in hfcpci_clear_fifo_rx()
336 hc->hw.fifo_en ^= fifo_state; in hfcpci_clear_fifo_rx()
337 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); in hfcpci_clear_fifo_rx()
338 hc->hw.last_bfifo_cnt[fifo] = 0; in hfcpci_clear_fifo_rx()
345 hc->hw.fifo_en |= fifo_state; in hfcpci_clear_fifo_rx()
346 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); in hfcpci_clear_fifo_rx()
352 static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo) in hfcpci_clear_fifo_tx() argument
358 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2; in hfcpci_clear_fifo_tx()
359 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX; in hfcpci_clear_fifo_tx()
361 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1; in hfcpci_clear_fifo_tx()
362 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX; in hfcpci_clear_fifo_tx()
365 hc->hw.fifo_en ^= fifo_state; in hfcpci_clear_fifo_tx()
366 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); in hfcpci_clear_fifo_tx()
367 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL) in hfcpci_clear_fifo_tx()
379 hc->hw.fifo_en |= fifo_state; in hfcpci_clear_fifo_tx()
380 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); in hfcpci_clear_fifo_tx()
381 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL) in hfcpci_clear_fifo_tx()
452 receive_dmsg(struct hfc_pci *hc) in receive_dmsg() argument
454 struct dchannel *dch = &hc->dch; in receive_dmsg()
462 df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx; in receive_dmsg()
600 struct hfc_pci *hc = bch->hw; in main_rec_hfcpci() local
607 if ((bch->nr & 2) && (!hc->hw.bswapped)) { in main_rec_hfcpci()
608 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2; in main_rec_hfcpci()
609 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2; in main_rec_hfcpci()
610 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2; in main_rec_hfcpci()
613 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1; in main_rec_hfcpci()
614 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1; in main_rec_hfcpci()
615 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1; in main_rec_hfcpci()
639 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) { in main_rec_hfcpci()
641 hfcpci_clear_fifo_rx(hc, real_fifo); in main_rec_hfcpci()
643 hc->hw.last_bfifo_cnt[real_fifo] = rcnt; in main_rec_hfcpci()
662 hfcpci_fill_dfifo(struct hfc_pci *hc) in hfcpci_fill_dfifo() argument
664 struct dchannel *dch = &hc->dch; in hfcpci_fill_dfifo()
678 df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx; in hfcpci_fill_dfifo()
741 struct hfc_pci *hc = bch->hw; in hfcpci_fill_fifo() local
759 if ((bch->nr & 2) && (!hc->hw.bswapped)) { in hfcpci_fill_fifo()
760 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2; in hfcpci_fill_fifo()
761 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2; in hfcpci_fill_fifo()
763 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1; in hfcpci_fill_fifo()
764 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1; in hfcpci_fill_fifo()
940 struct hfc_pci *hc = dch->hw; in handle_nt_timer3() local
943 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER; in handle_nt_timer3()
944 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); in handle_nt_timer3()
945 hc->hw.nt_timer = 0; in handle_nt_timer3()
947 if (test_bit(HFC_CFG_MASTER, &hc->cfg)) in handle_nt_timer3()
948 hc->hw.mst_m |= HFCPCI_MASTER; in handle_nt_timer3()
949 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); in handle_nt_timer3()
957 struct hfc_pci *hc = dch->hw; in ph_state_nt() local
964 if (hc->hw.nt_timer < 0) { in ph_state_nt()
965 hc->hw.nt_timer = 0; in ph_state_nt()
968 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER; in ph_state_nt()
969 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); in ph_state_nt()
971 (void) Read_hfc(hc, HFCPCI_INT_S1); in ph_state_nt()
972 Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE); in ph_state_nt()
974 Write_hfc(hc, HFCPCI_STATES, 4); in ph_state_nt()
976 } else if (hc->hw.nt_timer == 0) { in ph_state_nt()
977 hc->hw.int_m1 |= HFCPCI_INTS_TIMER; in ph_state_nt()
978 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); in ph_state_nt()
979 hc->hw.nt_timer = NT_T1_COUNT; in ph_state_nt()
980 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER; in ph_state_nt()
981 hc->hw.ctmt |= HFCPCI_TIM3_125; in ph_state_nt()
982 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | in ph_state_nt()
987 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3); in ph_state_nt()
989 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3); in ph_state_nt()
993 hc->hw.nt_timer = 0; in ph_state_nt()
996 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER; in ph_state_nt()
997 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); in ph_state_nt()
999 hc->hw.mst_m &= ~HFCPCI_MASTER; in ph_state_nt()
1000 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); in ph_state_nt()
1006 hc->hw.nt_timer = 0; in ph_state_nt()
1009 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER; in ph_state_nt()
1010 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); in ph_state_nt()
1020 hc->hw.int_m1 |= HFCPCI_INTS_TIMER; in ph_state_nt()
1021 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); in ph_state_nt()
1022 hc->hw.nt_timer = NT_T3_COUNT; in ph_state_nt()
1023 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER; in ph_state_nt()
1024 hc->hw.ctmt |= HFCPCI_TIM3_125; in ph_state_nt()
1025 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | in ph_state_nt()
1035 struct hfc_pci *hc = dch->hw; in ph_state() local
1037 if (hc->hw.protocol == ISDN_P_NT_S0) { in ph_state()
1039 hc->hw.nt_timer < 0) in ph_state()
1053 struct hfc_pci *hc = dch->hw; in hfc_l1callback() local
1058 if (test_bit(HFC_CFG_MASTER, &hc->cfg)) in hfc_l1callback()
1059 hc->hw.mst_m |= HFCPCI_MASTER; in hfc_l1callback()
1060 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); in hfc_l1callback()
1063 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3); in hfc_l1callback()
1066 Write_hfc(hc, HFCPCI_STATES, 3); /* HFC ST 2 */ in hfc_l1callback()
1067 if (test_bit(HFC_CFG_MASTER, &hc->cfg)) in hfc_l1callback()
1068 hc->hw.mst_m |= HFCPCI_MASTER; in hfc_l1callback()
1069 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); in hfc_l1callback()
1070 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE | in hfc_l1callback()
1075 hc->hw.mst_m &= ~HFCPCI_MASTER; in hfc_l1callback()
1076 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); in hfc_l1callback()
1092 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION); in hfc_l1callback()
1143 struct hfc_pci *hc = dev_id; in hfcpci_int() local
1148 spin_lock(&hc->lock); in hfcpci_int()
1149 if (!(hc->hw.int_m2 & 0x08)) { in hfcpci_int()
1150 spin_unlock(&hc->lock); in hfcpci_int()
1153 stat = Read_hfc(hc, HFCPCI_STATUS); in hfcpci_int()
1155 val = Read_hfc(hc, HFCPCI_INT_S1); in hfcpci_int()
1156 if (hc->dch.debug & DEBUG_HW_DCHANNEL) in hfcpci_int()
1161 spin_unlock(&hc->lock); in hfcpci_int()
1164 hc->irqcnt++; in hfcpci_int()
1166 if (hc->dch.debug & DEBUG_HW_DCHANNEL) in hfcpci_int()
1168 val &= hc->hw.int_m1; in hfcpci_int()
1170 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf; in hfcpci_int()
1171 if (hc->dch.debug & DEBUG_HW_DCHANNEL) in hfcpci_int()
1173 hc->dch.state, exval); in hfcpci_int()
1174 hc->dch.state = exval; in hfcpci_int()
1175 schedule_event(&hc->dch, FLG_PHCHANGE); in hfcpci_int()
1179 if (hc->hw.protocol == ISDN_P_NT_S0) { in hfcpci_int()
1180 if ((--hc->hw.nt_timer) < 0) in hfcpci_int()
1181 schedule_event(&hc->dch, FLG_PHCHANGE); in hfcpci_int()
1184 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER); in hfcpci_int()
1187 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1); in hfcpci_int()
1190 else if (hc->dch.debug) in hfcpci_int()
1194 bch = Sel_BCS(hc, 2); in hfcpci_int()
1197 else if (hc->dch.debug) in hfcpci_int()
1201 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1); in hfcpci_int()
1204 else if (hc->dch.debug) in hfcpci_int()
1208 bch = Sel_BCS(hc, 2); in hfcpci_int()
1211 else if (hc->dch.debug) in hfcpci_int()
1215 receive_dmsg(hc); in hfcpci_int()
1217 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags)) in hfcpci_int()
1218 del_timer(&hc->dch.timer); in hfcpci_int()
1219 tx_dirq(&hc->dch); in hfcpci_int()
1221 spin_unlock(&hc->lock); in hfcpci_int()
1239 struct hfc_pci *hc = bch->hw; in mode_hfcpci() local
1251 if (!test_bit(HFC_CFG_PCM, &hc->cfg)) in mode_hfcpci()
1258 } else if (test_bit(HFC_CFG_PCM, &hc->cfg) && (protocol > ISDN_P_NONE)) in mode_hfcpci()
1261 if (hc->chanlimit > 1) { in mode_hfcpci()
1262 hc->hw.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcpci()
1263 hc->hw.sctrl_e &= ~0x80; in mode_hfcpci()
1267 hc->hw.bswapped = 1; /* B1 and B2 exchanged */ in mode_hfcpci()
1268 hc->hw.sctrl_e |= 0x80; in mode_hfcpci()
1270 hc->hw.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcpci()
1271 hc->hw.sctrl_e &= ~0x80; in mode_hfcpci()
1275 hc->hw.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcpci()
1276 hc->hw.sctrl_e &= ~0x80; in mode_hfcpci()
1288 hc->hw.sctrl &= ~SCTRL_B2_ENA; in mode_hfcpci()
1289 hc->hw.sctrl_r &= ~SCTRL_B2_ENA; in mode_hfcpci()
1291 hc->hw.sctrl &= ~SCTRL_B1_ENA; in mode_hfcpci()
1292 hc->hw.sctrl_r &= ~SCTRL_B1_ENA; in mode_hfcpci()
1295 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2; in mode_hfcpci()
1296 hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS | in mode_hfcpci()
1299 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1; in mode_hfcpci()
1300 hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS | in mode_hfcpci()
1305 hc->hw.cirm &= 0x7f; in mode_hfcpci()
1307 hc->hw.cirm &= 0xbf; in mode_hfcpci()
1317 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0); in mode_hfcpci()
1318 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0); in mode_hfcpci()
1320 hc->hw.sctrl |= SCTRL_B2_ENA; in mode_hfcpci()
1321 hc->hw.sctrl_r |= SCTRL_B2_ENA; in mode_hfcpci()
1323 hc->hw.cirm |= 0x80; in mode_hfcpci()
1326 hc->hw.sctrl |= SCTRL_B1_ENA; in mode_hfcpci()
1327 hc->hw.sctrl_r |= SCTRL_B1_ENA; in mode_hfcpci()
1329 hc->hw.cirm |= 0x40; in mode_hfcpci()
1333 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2; in mode_hfcpci()
1335 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS | in mode_hfcpci()
1337 hc->hw.ctmt |= 2; in mode_hfcpci()
1338 hc->hw.conn &= ~0x18; in mode_hfcpci()
1340 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1; in mode_hfcpci()
1342 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS | in mode_hfcpci()
1344 hc->hw.ctmt |= 1; in mode_hfcpci()
1345 hc->hw.conn &= ~0x03; in mode_hfcpci()
1352 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0); in mode_hfcpci()
1353 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0); in mode_hfcpci()
1355 hc->hw.sctrl |= SCTRL_B2_ENA; in mode_hfcpci()
1356 hc->hw.sctrl_r |= SCTRL_B2_ENA; in mode_hfcpci()
1358 hc->hw.sctrl |= SCTRL_B1_ENA; in mode_hfcpci()
1359 hc->hw.sctrl_r |= SCTRL_B1_ENA; in mode_hfcpci()
1362 hc->hw.last_bfifo_cnt[1] = 0; in mode_hfcpci()
1363 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2; in mode_hfcpci()
1364 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS | in mode_hfcpci()
1366 hc->hw.ctmt &= ~2; in mode_hfcpci()
1367 hc->hw.conn &= ~0x18; in mode_hfcpci()
1369 hc->hw.last_bfifo_cnt[0] = 0; in mode_hfcpci()
1370 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1; in mode_hfcpci()
1371 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS | in mode_hfcpci()
1373 hc->hw.ctmt &= ~1; in mode_hfcpci()
1374 hc->hw.conn &= ~0x03; in mode_hfcpci()
1382 if (test_bit(HFC_CFG_PCM, &hc->cfg)) { in mode_hfcpci()
1388 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) { in mode_hfcpci()
1397 hc->hw.conn &= 0xc7; in mode_hfcpci()
1398 hc->hw.conn |= 0x08; in mode_hfcpci()
1403 Write_hfc(hc, HFCPCI_B2_SSL, tx_slot); in mode_hfcpci()
1404 Write_hfc(hc, HFCPCI_B2_RSL, rx_slot); in mode_hfcpci()
1406 hc->hw.conn &= 0xf8; in mode_hfcpci()
1407 hc->hw.conn |= 0x01; in mode_hfcpci()
1412 Write_hfc(hc, HFCPCI_B1_SSL, tx_slot); in mode_hfcpci()
1413 Write_hfc(hc, HFCPCI_B1_RSL, rx_slot); in mode_hfcpci()
1416 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e); in mode_hfcpci()
1417 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); in mode_hfcpci()
1418 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); in mode_hfcpci()
1419 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl); in mode_hfcpci()
1420 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r); in mode_hfcpci()
1421 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt); in mode_hfcpci()
1422 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); in mode_hfcpci()
1424 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm); in mode_hfcpci()
1432 struct hfc_pci *hc = bch->hw; in set_hfcpci_rxtest() local
1447 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0); in set_hfcpci_rxtest()
1449 hc->hw.sctrl_r |= SCTRL_B2_ENA; in set_hfcpci_rxtest()
1450 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX; in set_hfcpci_rxtest()
1452 hc->hw.int_m1 |= HFCPCI_INTS_B2REC; in set_hfcpci_rxtest()
1453 hc->hw.ctmt |= 2; in set_hfcpci_rxtest()
1454 hc->hw.conn &= ~0x18; in set_hfcpci_rxtest()
1456 hc->hw.cirm |= 0x80; in set_hfcpci_rxtest()
1459 hc->hw.sctrl_r |= SCTRL_B1_ENA; in set_hfcpci_rxtest()
1460 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX; in set_hfcpci_rxtest()
1462 hc->hw.int_m1 |= HFCPCI_INTS_B1REC; in set_hfcpci_rxtest()
1463 hc->hw.ctmt |= 1; in set_hfcpci_rxtest()
1464 hc->hw.conn &= ~0x03; in set_hfcpci_rxtest()
1466 hc->hw.cirm |= 0x40; in set_hfcpci_rxtest()
1472 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0); in set_hfcpci_rxtest()
1474 hc->hw.sctrl_r |= SCTRL_B2_ENA; in set_hfcpci_rxtest()
1475 hc->hw.last_bfifo_cnt[1] = 0; in set_hfcpci_rxtest()
1476 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX; in set_hfcpci_rxtest()
1477 hc->hw.int_m1 |= HFCPCI_INTS_B2REC; in set_hfcpci_rxtest()
1478 hc->hw.ctmt &= ~2; in set_hfcpci_rxtest()
1479 hc->hw.conn &= ~0x18; in set_hfcpci_rxtest()
1481 hc->hw.sctrl_r |= SCTRL_B1_ENA; in set_hfcpci_rxtest()
1482 hc->hw.last_bfifo_cnt[0] = 0; in set_hfcpci_rxtest()
1483 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX; in set_hfcpci_rxtest()
1484 hc->hw.int_m1 |= HFCPCI_INTS_B1REC; in set_hfcpci_rxtest()
1485 hc->hw.ctmt &= ~1; in set_hfcpci_rxtest()
1486 hc->hw.conn &= ~0x03; in set_hfcpci_rxtest()
1493 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); in set_hfcpci_rxtest()
1494 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en); in set_hfcpci_rxtest()
1495 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r); in set_hfcpci_rxtest()
1496 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt); in set_hfcpci_rxtest()
1497 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); in set_hfcpci_rxtest()
1499 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm); in set_hfcpci_rxtest()
1507 struct hfc_pci *hc = bch->hw; in deactivate_bchannel() local
1510 spin_lock_irqsave(&hc->lock, flags); in deactivate_bchannel()
1513 spin_unlock_irqrestore(&hc->lock, flags); in deactivate_bchannel()
1528 struct hfc_pci *hc = bch->hw; in hfc_bctrl() local
1536 spin_lock_irqsave(&hc->lock, flags); in hfc_bctrl()
1538 spin_unlock_irqrestore(&hc->lock, flags); in hfc_bctrl()
1541 spin_lock_irqsave(&hc->lock, flags); in hfc_bctrl()
1543 spin_unlock_irqrestore(&hc->lock, flags); in hfc_bctrl()
1546 spin_lock_irqsave(&hc->lock, flags); in hfc_bctrl()
1548 spin_unlock_irqrestore(&hc->lock, flags); in hfc_bctrl()
1577 struct hfc_pci *hc = dch->hw; in hfcpci_l2l1D() local
1585 spin_lock_irqsave(&hc->lock, flags); in hfcpci_l2l1D()
1591 spin_unlock_irqrestore(&hc->lock, flags); in hfcpci_l2l1D()
1594 spin_unlock_irqrestore(&hc->lock, flags); in hfcpci_l2l1D()
1597 spin_lock_irqsave(&hc->lock, flags); in hfcpci_l2l1D()
1598 if (hc->hw.protocol == ISDN_P_NT_S0) { in hfcpci_l2l1D()
1600 if (test_bit(HFC_CFG_MASTER, &hc->cfg)) in hfcpci_l2l1D()
1601 hc->hw.mst_m |= HFCPCI_MASTER; in hfcpci_l2l1D()
1602 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); in hfcpci_l2l1D()
1604 spin_unlock_irqrestore(&hc->lock, flags); in hfcpci_l2l1D()
1610 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE | in hfcpci_l2l1D()
1614 spin_unlock_irqrestore(&hc->lock, flags); in hfcpci_l2l1D()
1618 spin_lock_irqsave(&hc->lock, flags); in hfcpci_l2l1D()
1619 if (hc->hw.protocol == ISDN_P_NT_S0) { in hfcpci_l2l1D()
1624 Write_hfc(hc, HFCPCI_STATES, 0x40); in hfcpci_l2l1D()
1640 dchannel_sched_event(&hc->dch, D_CLEARBUSY); in hfcpci_l2l1D()
1642 hc->hw.mst_m &= ~HFCPCI_MASTER; in hfcpci_l2l1D()
1643 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); in hfcpci_l2l1D()
1645 spin_unlock_irqrestore(&hc->lock, flags); in hfcpci_l2l1D()
1649 spin_unlock_irqrestore(&hc->lock, flags); in hfcpci_l2l1D()
1665 struct hfc_pci *hc = bch->hw; in hfcpci_l2l1B() local
1672 spin_lock_irqsave(&hc->lock, flags); in hfcpci_l2l1B()
1678 spin_unlock_irqrestore(&hc->lock, flags); in hfcpci_l2l1B()
1681 spin_lock_irqsave(&hc->lock, flags); in hfcpci_l2l1B()
1686 spin_unlock_irqrestore(&hc->lock, flags); in hfcpci_l2l1B()
1708 inithfcpci(struct hfc_pci *hc) in inithfcpci() argument
1711 timer_setup(&hc->dch.timer, hfcpci_dbusy_timer, 0); in inithfcpci()
1712 hc->chanlimit = 2; in inithfcpci()
1713 mode_hfcpci(&hc->bch[0], 1, -1); in inithfcpci()
1714 mode_hfcpci(&hc->bch[1], 2, -1); in inithfcpci()
1719 init_card(struct hfc_pci *hc) in init_card() argument
1727 spin_lock_irqsave(&hc->lock, flags); in init_card()
1728 disable_hwirq(hc); in init_card()
1729 spin_unlock_irqrestore(&hc->lock, flags); in init_card()
1730 if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) { in init_card()
1732 "mISDN: couldn't get interrupt %d\n", hc->irq); in init_card()
1735 spin_lock_irqsave(&hc->lock, flags); in init_card()
1736 reset_hfcpci(hc); in init_card()
1738 inithfcpci(hc); in init_card()
1744 enable_hwirq(hc); in init_card()
1745 spin_unlock_irqrestore(&hc->lock, flags); in init_card()
1750 hc->irq, hc->irqcnt); in init_card()
1752 spin_lock_irqsave(&hc->lock, flags); in init_card()
1753 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER; in init_card()
1754 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); in init_card()
1756 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m); in init_card()
1757 if (!hc->irqcnt) { in init_card()
1760 "during init %d\n", hc->irq, 4 - cnt); in init_card()
1764 reset_hfcpci(hc); in init_card()
1768 spin_unlock_irqrestore(&hc->lock, flags); in init_card()
1769 hc->initdone = 1; in init_card()
1773 disable_hwirq(hc); in init_card()
1774 spin_unlock_irqrestore(&hc->lock, flags); in init_card()
1775 free_irq(hc->irq, hc); in init_card()
1780 channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq) in channel_ctrl() argument
1797 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) in channel_ctrl()
1803 Write_hfc(hc, HFCPCI_B1_SSL, slot); in channel_ctrl()
1804 Write_hfc(hc, HFCPCI_B1_RSL, slot); in channel_ctrl()
1805 hc->hw.conn = (hc->hw.conn & ~7) | 6; in channel_ctrl()
1806 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); in channel_ctrl()
1809 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) in channel_ctrl()
1815 Write_hfc(hc, HFCPCI_B2_SSL, slot); in channel_ctrl()
1816 Write_hfc(hc, HFCPCI_B2_RSL, slot); in channel_ctrl()
1817 hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30; in channel_ctrl()
1818 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); in channel_ctrl()
1821 hc->hw.trm |= 0x80; /* enable IOM-loop */ in channel_ctrl()
1823 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09; in channel_ctrl()
1824 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); in channel_ctrl()
1825 hc->hw.trm &= 0x7f; /* disable IOM-loop */ in channel_ctrl()
1827 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm); in channel_ctrl()
1839 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) in channel_ctrl()
1845 Write_hfc(hc, HFCPCI_B1_SSL, slot); in channel_ctrl()
1846 Write_hfc(hc, HFCPCI_B2_RSL, slot); in channel_ctrl()
1847 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) in channel_ctrl()
1853 Write_hfc(hc, HFCPCI_B2_SSL, slot); in channel_ctrl()
1854 Write_hfc(hc, HFCPCI_B1_RSL, slot); in channel_ctrl()
1855 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36; in channel_ctrl()
1856 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); in channel_ctrl()
1857 hc->hw.trm |= 0x80; in channel_ctrl()
1858 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm); in channel_ctrl()
1861 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09; in channel_ctrl()
1862 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn); in channel_ctrl()
1863 hc->hw.trm &= 0x7f; /* disable IOM-loop */ in channel_ctrl()
1866 ret = l1_event(hc->dch.l1, HW_TIMER3_VALUE | (cq->p1 & 0xff)); in channel_ctrl()
1878 open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch, in open_dchannel() argument
1885 hc->dch.dev.id, __builtin_return_address(0)); in open_dchannel()
1892 if (!hc->initdone) { in open_dchannel()
1894 err = create_l1(&hc->dch, hfc_l1callback); in open_dchannel()
1898 hc->hw.protocol = rq->protocol; in open_dchannel()
1900 err = init_card(hc); in open_dchannel()
1905 if (hc->hw.protocol == ISDN_P_TE_S0) in open_dchannel()
1906 l1_event(hc->dch.l1, CLOSE_CHANNEL); in open_dchannel()
1908 err = create_l1(&hc->dch, hfc_l1callback); in open_dchannel()
1912 hc->hw.protocol = rq->protocol; in open_dchannel()
1914 hfcpci_setmode(hc); in open_dchannel()
1918 if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) || in open_dchannel()
1919 ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) { in open_dchannel()
1930 open_bchannel(struct hfc_pci *hc, struct channel_req *rq) in open_bchannel() argument
1938 bch = &hc->bch[rq->adr.channel - 1]; in open_bchannel()
1956 struct hfc_pci *hc = dch->hw; in hfc_dctrl() local
1968 err = open_dchannel(hc, ch, rq); in hfc_dctrl()
1970 err = open_bchannel(hc, rq); in hfc_dctrl()
1975 __func__, hc->dch.dev.id, in hfc_dctrl()
1980 err = channel_ctrl(hc, arg); in hfc_dctrl()
1992 setup_hw(struct hfc_pci *hc) in setup_hw() argument
1997 hc->hw.cirm = 0; in setup_hw()
1998 hc->dch.state = 0; in setup_hw()
1999 pci_set_master(hc->pdev); in setup_hw()
2000 if (!hc->irq) { in setup_hw()
2004 hc->hw.pci_io = in setup_hw()
2005 (char __iomem *)(unsigned long)hc->pdev->resource[1].start; in setup_hw()
2007 if (!hc->hw.pci_io) { in setup_hw()
2013 if (dma_set_mask(&hc->pdev->dev, 0xFFFF8000)) { in setup_hw()
2018 buffer = dma_alloc_coherent(&hc->pdev->dev, 0x8000, &hc->hw.dmahandle, in setup_hw()
2026 hc->hw.fifos = buffer; in setup_hw()
2027 pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle); in setup_hw()
2028 hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256); in setup_hw()
2029 if (unlikely(!hc->hw.pci_io)) { in setup_hw()
2032 dma_free_coherent(&hc->pdev->dev, 0x8000, hc->hw.fifos, in setup_hw()
2033 hc->hw.dmahandle); in setup_hw()
2039 (u_long) hc->hw.pci_io, hc->hw.fifos, in setup_hw()
2040 &hc->hw.dmahandle, hc->irq, HZ); in setup_hw()
2043 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO); in setup_hw()
2044 hc->hw.int_m2 = 0; in setup_hw()
2045 disable_hwirq(hc); in setup_hw()
2046 hc->hw.int_m1 = 0; in setup_hw()
2047 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1); in setup_hw()
2050 timer_setup(&hc->hw.timer, hfcpci_Timer, 0); in setup_hw()
2052 test_and_set_bit(HFC_CFG_MASTER, &hc->cfg); in setup_hw()
2057 release_card(struct hfc_pci *hc) { in release_card() argument
2060 spin_lock_irqsave(&hc->lock, flags); in release_card()
2061 hc->hw.int_m2 = 0; /* interrupt output off ! */ in release_card()
2062 disable_hwirq(hc); in release_card()
2063 mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE); in release_card()
2064 mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE); in release_card()
2065 if (hc->dch.timer.function != NULL) { in release_card()
2066 del_timer(&hc->dch.timer); in release_card()
2067 hc->dch.timer.function = NULL; in release_card()
2069 spin_unlock_irqrestore(&hc->lock, flags); in release_card()
2070 if (hc->hw.protocol == ISDN_P_TE_S0) in release_card()
2071 l1_event(hc->dch.l1, CLOSE_CHANNEL); in release_card()
2072 if (hc->initdone) in release_card()
2073 free_irq(hc->irq, hc); in release_card()
2074 release_io_hfcpci(hc); /* must release after free_irq! */ in release_card()
2075 mISDN_unregister_device(&hc->dch.dev); in release_card()
2076 mISDN_freebchannel(&hc->bch[1]); in release_card()
2077 mISDN_freebchannel(&hc->bch[0]); in release_card()
2078 mISDN_freedchannel(&hc->dch); in release_card()
2079 pci_set_drvdata(hc->pdev, NULL); in release_card()
2080 kfree(hc); in release_card()
2274 struct hfc_pci *hc = dev_get_drvdata(dev); in _hfcpci_softirq() local
2276 if (hc == NULL) in _hfcpci_softirq()
2279 if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) { in _hfcpci_softirq()
2280 spin_lock(&hc->lock); in _hfcpci_softirq()
2281 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1); in _hfcpci_softirq()
2286 bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2); in _hfcpci_softirq()
2291 spin_unlock(&hc->lock); in _hfcpci_softirq()