Lines Matching refs:regoff
85 u16 regoff; member
477 read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3); in get_cur_symbol_rate()
478 read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2); in get_cur_symbol_rate()
479 read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1); in get_cur_symbol_rate()
480 read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0); in get_cur_symbol_rate()
481 read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2); in get_cur_symbol_rate()
482 read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1); in get_cur_symbol_rate()
483 read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0); in get_cur_symbol_rate()
509 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); in get_signal_parameters()
515 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); in get_signal_parameters()
545 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp); in tracking_optimization()
559 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp); in tracking_optimization()
573 state->regoff, aclc); in tracking_optimization()
576 state->regoff, 0x2a); in tracking_optimization()
578 state->regoff, aclc); in tracking_optimization()
581 state->regoff, 0x2a); in tracking_optimization()
583 state->regoff, aclc); in tracking_optimization()
586 state->regoff, 0x2a); in tracking_optimization()
588 state->regoff, aclc); in tracking_optimization()
645 read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff, in get_signal_to_noise()
647 read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff, in get_signal_to_noise()
652 read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff, in get_signal_to_noise()
654 read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff, in get_signal_to_noise()
670 RSTV0910_P2_ERRCNT12 + state->regoff, in get_bit_error_rate_s()
684 state->regoff, in get_bit_error_rate_s()
690 state->regoff, 0x20 | in get_bit_error_rate_s()
744 int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff, in get_bit_error_rate_s2()
759 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, in get_bit_error_rate_s2()
764 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff, in get_bit_error_rate_s2()
860 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in stop()
862 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp); in stop()
864 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp); in stop()
866 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B); in stop()
868 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c); in stop()
881 write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff, in set_pls()
883 write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff, in set_pls()
885 write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff, in set_pls()
899 write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff, in set_isi()
901 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff); in set_isi()
958 return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val); in enable_puncture_rate()
969 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth_default()
970 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth_default()
971 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth_default()
972 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth_default()
973 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth_default()
974 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth_default()
991 RSTV0910_P2_NNOSDATAT1 + state->regoff, in set_vth()
1001 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth()
1002 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]); in set_vth()
1003 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]); in set_vth()
1004 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]); in set_vth()
1005 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]); in set_vth()
1006 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]); in set_vth()
1024 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C); in start()
1050 write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff, in start()
1052 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF)); in start()
1055 write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits); in start()
1058 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®_dmdcfgmd); in start()
1059 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, in start()
1066 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00); in start()
1067 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F); in start()
1072 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B); in start()
1073 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A); in start()
1074 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84); in start()
1075 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84); in start()
1076 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C); in start()
1077 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79); in start()
1079 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29); in start()
1080 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09); in start()
1081 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84); in start()
1082 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84); in start()
1093 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1095 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46); in start()
1103 write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff, in start()
1105 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff)); in start()
1108 write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff, in start()
1110 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff)); in start()
1113 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0); in start()
1114 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0); in start()
1116 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1118 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15); in start()
1297 read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff, in manage_matype_info()
1352 read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2); in read_signal_strength()
1357 read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2); in read_signal_strength()
1381 read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state); in read_status()
1384 read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus); in read_status()
1414 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1417 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1419 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, in read_status()
1427 RSTV0910_P2_PDELSTATUS1 + state->regoff, in read_status()
1434 RSTV0910_P2_VSTATUSVIT + state->regoff, in read_status()
1457 RSTV0910_P2_DEMOD + state->regoff, in read_status()
1460 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1465 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1470 RSTV0910_P2_PDELCTRL2 + state->regoff, in read_status()
1478 RSTV0910_P2_ERRCTRL1 + state->regoff, in read_status()
1486 RSTV0910_P2_ERRCTRL1 + state->regoff, in read_status()
1491 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00); in read_status()
1497 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1); in read_status()
1510 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, in read_status()
1570 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); in get_frontend()
1576 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); in get_frontend()
1784 state->regoff = state->nr ? 0 : 0x200; in stv0910_attach()