Lines Matching refs:REGS
675 #define REGS(...) REGS_ENTRY(((const __be16[]){__VA_ARGS__})) macro
681 REGS(be(0x0112), be(0x0808)), /* 8-bit/8-bit mode */
684 REGS(be(0x301E), be(0x00AA)),
687 REGS(be(0x3042),
691 REGS(be(0x30D2),
697 REGS(be(0x30DA),
703 REGS(be(0x30EE), be(0x1136)),
704 REGS(be(0x30FA), be(0xFD00)), /* GPIO0 = flash, GPIO1 = shutter */
705 REGS(be(0x3120), be(0x0005)), /* p1 dither enabled for 10bit mode */
706 REGS(be(0x3172), be(0x0206)), /* txlo clk divider options */
708 REGS(be(0x3180), be(0x9434)),
710 REGS(be(0x31B0),
715 REGS(be(0x31BC), be(0x068C)),
716 REGS(be(0x31E0), be(0x0781)), /* Fuse/2DDC: enable 2ddc */
719 REGS(be(0x341A), be(0x4735)), /* Samp&Hold pulse in ADC */
720 REGS(be(0x3420), be(0x4735)), /* Samp&Hold pulse in ADC */
721 REGS(be(0x3426), be(0x8A1A)), /* ADC offset distribution pulse */
722 REGS(be(0x342A), be(0x0018)), /* pulse_config */
725 REGS(be(0x3D00),
782 REGS(be(0x3EB6), be(0x004C)), /* ECL */
784 REGS(be(0x3EBA),
788 REGS(be(0x3EC0),
809 REGS(be(0x3F00),
822 REGS(be(0x3F10),
832 REGS(be(0x3F2C), be(0x442E)),
834 REGS(be(0x3F3E),