Lines Matching refs:netup_fpga_op_rw
249 static int netup_fpga_op_rw(struct fpga_internal *inter, int addr, in netup_fpga_op_rw() function
272 netup_fpga_op_rw(inter, NETUP_CI_ADDR0, ((addr << 1) & 0xfe), 0); in altera_ci_op_cam()
273 netup_fpga_op_rw(inter, NETUP_CI_ADDR1, ((addr >> 7) & 0x7f), 0); in altera_ci_op_cam()
274 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in altera_ci_op_cam()
279 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, store, 0); in altera_ci_op_cam()
280 mem = netup_fpga_op_rw(inter, NETUP_CI_DATA, val, read); in altera_ci_op_cam()
332 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in altera_ci_slot_reset()
333 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, in altera_ci_slot_reset()
343 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, in altera_ci_slot_reset()
379 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in altera_ci_slot_ts_ctl()
380 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, in altera_ci_slot_ts_ctl()
399 ret = netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0, NETUP_CI_FLG_RD); in netup_read_ci_status()
400 ret = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL, 0, NETUP_CI_FLG_RD); in netup_read_ci_status()
526 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, (pid >> 3) & 0xff, 0); in altera_pid_control()
527 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1, in altera_pid_control()
530 store = netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, 0, NETUP_CI_FLG_RD); in altera_pid_control()
537 netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, store, 0); in altera_pid_control()
563 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR0, i & 0xff, 0); in altera_toggle_fullts_streaming()
565 netup_fpga_op_rw(inter, NETUP_CI_PID_ADDR1, in altera_toggle_fullts_streaming()
568 netup_fpga_op_rw(inter, NETUP_CI_PID_DATA, in altera_toggle_fullts_streaming()
780 netup_fpga_op_rw(inter, NETUP_CI_TSA_DIV, 0x0, 0); in altera_ci_init()
781 netup_fpga_op_rw(inter, NETUP_CI_TSB_DIV, 0x0, 0); in altera_ci_init()
784 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD); in altera_ci_init()
786 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0); in altera_ci_init()
788 ret = netup_fpga_op_rw(inter, NETUP_CI_REVISION, 0, NETUP_CI_FLG_RD); in altera_ci_init()
790 netup_fpga_op_rw(inter, NETUP_CI_INT_CTRL, 0x44, 0); in altera_ci_init()
827 store = netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, 0, NETUP_CI_FLG_RD); in altera_ci_tuner_reset()
829 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0); in altera_ci_tuner_reset()
832 netup_fpga_op_rw(inter, NETUP_CI_BUSCTRL2, store, 0); in altera_ci_tuner_reset()